1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
15 * GNU General public License for more details. *
17 * You should have received a copy of the GNU General public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ****************************************************************************/
23 /***************************************************************************
25 * New flash setup command:
27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
28 * [<chip_type> <banks>
29 * <sectors_per_bank> <pages_per_sector>
30 * <page_size> <num_nvmbits>
33 * <ext_freq_khz> - MUST be used if clock is from external source,
34 * CAN be used if main oscillator frequency is known (recommended)
36 * ==== RECOMMENDED (covers clock speed) ============
37 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
38 * (if auto-detect fails; provides clock spec)
39 * flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
40 * (auto-detect everything except the clock)
41 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
42 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
43 * (if auto-detect fails)
44 * flash bank at91sam7 0 0 0 0 $_TARGETNAME
45 * (old style, auto-detect everything)
46 ****************************************************************************/
53 #include <helper/binarybuffer.h>
56 /* AT91SAM7 control registers */
57 #define DBGU_CIDR 0xFFFFF240
58 #define CKGR_MCFR 0xFFFFFC24
59 #define CKGR_MOR 0xFFFFFC20
60 #define CKGR_MCFR_MAINRDY 0x10000
61 #define CKGR_PLLR 0xFFFFFC2c
62 #define CKGR_PLLR_DIV 0xff
63 #define CKGR_PLLR_MUL 0x07ff0000
64 #define PMC_MCKR 0xFFFFFC30
65 #define PMC_MCKR_CSS 0x03
66 #define PMC_MCKR_PRES 0x1c
68 /* Flash Controller Commands */
78 /* MC_FSR bit definitions */
82 /* AT91SAM7 constants */
85 /* Flash timing modes */
86 #define FMR_TIMING_NONE 0
87 #define FMR_TIMING_NVBITS 1
88 #define FMR_TIMING_FLASH 2
90 /* Flash size constants */
91 #define FLASH_SIZE_8KB 1
92 #define FLASH_SIZE_16KB 2
93 #define FLASH_SIZE_32KB 3
94 #define FLASH_SIZE_64KB 5
95 #define FLASH_SIZE_128KB 7
96 #define FLASH_SIZE_256KB 9
97 #define FLASH_SIZE_512KB 10
98 #define FLASH_SIZE_1024KB 12
99 #define FLASH_SIZE_2048KB 14
102 static int at91sam7_protect_check(struct flash_bank
*bank
);
103 static int at91sam7_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
);
105 static uint32_t at91sam7_get_flash_status(struct target
*target
, int bank_number
);
106 static void at91sam7_set_flash_mode(struct flash_bank
*bank
, int mode
);
107 static uint32_t at91sam7_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
);
108 static int at91sam7_flash_command(struct flash_bank
*bank
, uint8_t cmd
, uint16_t pagen
);
110 static uint32_t MC_FMR
[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
111 static uint32_t MC_FCR
[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
112 static uint32_t MC_FSR
[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
114 static char * EPROC
[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
116 struct at91sam7_flash_bank
118 /* chip id register */
121 uint16_t cidr_nvptyp
;
123 uint16_t cidr_sramsiz
;
124 uint16_t cidr_nvpsiz
;
125 uint16_t cidr_nvpsiz2
;
127 uint16_t cidr_version
;
130 /* flash auto-detection */
131 uint8_t flash_autodetection
;
134 uint16_t pages_per_sector
;
136 uint16_t pages_in_lockregion
;
139 uint16_t num_lockbits_on
;
141 uint16_t num_nvmbits
;
142 uint16_t num_nvmbits_on
;
147 * 1: fmcn for nvbits (1uS)
148 * 2: fmcn for flash (1.5uS) */
151 /* main clock status */
155 /* external clock frequency */
161 static long SRAMSIZ
[16] = {
182 static uint32_t at91sam7_get_flash_status(struct target
*target
, int bank_number
)
185 target_read_u32(target
, MC_FSR
[bank_number
], &fsr
);
190 /* Read clock configuration and set at91sam7_info->mck_freq */
191 static void at91sam7_read_clock_info(struct flash_bank
*bank
)
193 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
194 struct target
*target
= bank
->target
;
195 uint32_t mckr
, mcfr
, pllr
, mor
;
196 unsigned long tmp
= 0, mainfreq
;
198 /* Read Clock Generator Main Oscillator Register */
199 target_read_u32(target
, CKGR_MOR
, &mor
);
200 /* Read Clock Generator Main Clock Frequency Register */
201 target_read_u32(target
, CKGR_MCFR
, &mcfr
);
202 /* Read Master Clock Register*/
203 target_read_u32(target
, PMC_MCKR
, &mckr
);
204 /* Read Clock Generator PLL Register */
205 target_read_u32(target
, CKGR_PLLR
, &pllr
);
207 at91sam7_info
->mck_valid
= 0;
208 at91sam7_info
->mck_freq
= 0;
209 switch (mckr
& PMC_MCKR_CSS
)
211 case 0: /* Slow Clock */
212 at91sam7_info
->mck_valid
= 1;
216 case 1: /* Main Clock */
217 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
218 (at91sam7_info
->ext_freq
== 0))
220 at91sam7_info
->mck_valid
= 1;
221 tmp
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
223 else if (at91sam7_info
->ext_freq
!= 0)
225 at91sam7_info
->mck_valid
= 1;
226 tmp
= at91sam7_info
->ext_freq
;
230 case 2: /* Reserved */
233 case 3: /* PLL Clock */
234 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
235 (at91sam7_info
->ext_freq
== 0))
237 target_read_u32(target
, CKGR_PLLR
, &pllr
);
238 if (!(pllr
& CKGR_PLLR_DIV
))
240 at91sam7_info
->mck_valid
= 1;
241 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
242 /* Integer arithmetic should have sufficient precision
243 * as long as PLL is properly configured. */
244 tmp
= mainfreq
/ (pllr
& CKGR_PLLR_DIV
)*
245 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
247 else if ((at91sam7_info
->ext_freq
!= 0) &&
248 ((pllr
&CKGR_PLLR_DIV
) != 0))
250 at91sam7_info
->mck_valid
= 1;
251 tmp
= at91sam7_info
->ext_freq
/ (pllr
&CKGR_PLLR_DIV
)*
252 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
257 /* Prescaler adjust */
258 if ((((mckr
& PMC_MCKR_PRES
) >> 2) == 7) || (tmp
== 0))
260 at91sam7_info
->mck_valid
= 0;
261 at91sam7_info
->mck_freq
= 0;
263 else if (((mckr
& PMC_MCKR_PRES
) >> 2) != 0)
264 at91sam7_info
->mck_freq
= tmp
>> ((mckr
& PMC_MCKR_PRES
) >> 2);
266 at91sam7_info
->mck_freq
= tmp
;
269 /* Setup the timimg registers for nvbits or normal flash */
270 static void at91sam7_set_flash_mode(struct flash_bank
*bank
, int mode
)
272 uint32_t fmr
, fmcn
= 0, fws
= 0;
273 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
274 struct target
*target
= bank
->target
;
276 if (mode
&& (mode
!= at91sam7_info
->flashmode
))
278 /* Always round up (ceil) */
279 if (mode
== FMR_TIMING_NVBITS
)
281 if (at91sam7_info
->cidr_arch
== 0x60)
283 /* AT91SAM7A3 uses master clocks in 100 ns */
284 fmcn
= (at91sam7_info
->mck_freq
/10000000ul) + 1;
288 /* master clocks in 1uS for ARCH 0x7 types */
289 fmcn
= (at91sam7_info
->mck_freq
/1000000ul) + 1;
292 else if (mode
== FMR_TIMING_FLASH
)
294 /* main clocks in 1.5uS */
295 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+
296 (at91sam7_info
->mck_freq
/2000000ul) + 1;
299 /* hard overclocking */
303 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
304 if (at91sam7_info
->mck_freq
<= 33333ul)
306 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
307 if (at91sam7_info
->mck_freq
> 30000000ul)
310 LOG_DEBUG("fmcn[%i]: %i", bank
->bank_number
, (int)(fmcn
));
311 fmr
= fmcn
<< 16 | fws
<< 8;
312 target_write_u32(target
, MC_FMR
[bank
->bank_number
], fmr
);
315 at91sam7_info
->flashmode
= mode
;
318 static uint32_t at91sam7_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
)
322 while ((!((status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
)) & waitbits
)) && (timeout
-- > 0))
324 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", (int)bank
->bank_number
, status
);
328 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", bank
->bank_number
, status
);
332 LOG_ERROR("status register: 0x%" PRIx32
"", status
);
334 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
336 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
338 LOG_ERROR("Security Bit Set, Operation Abort");
344 /* Send one command to the AT91SAM flash controller */
345 static int at91sam7_flash_command(struct flash_bank
*bank
, uint8_t cmd
, uint16_t pagen
)
348 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
349 struct target
*target
= bank
->target
;
351 fcr
= (0x5A << 24) | ((pagen
&0x3FF) << 8) | cmd
;
352 target_write_u32(target
, MC_FCR
[bank
->bank_number
], fcr
);
353 LOG_DEBUG("Flash command: 0x%" PRIx32
", flash bank: %i, page number: %u", fcr
, bank
->bank_number
+ 1, pagen
);
355 if ((at91sam7_info
->cidr_arch
== 0x60) && ((cmd
== SLB
) | (cmd
== CLB
)))
357 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
358 if (at91sam7_wait_status_busy(bank
, MC_FSR_EOL
, 10)&0x0C)
360 return ERROR_FLASH_OPERATION_FAILED
;
365 if (at91sam7_wait_status_busy(bank
, MC_FSR_FRDY
, 10)&0x0C)
367 return ERROR_FLASH_OPERATION_FAILED
;
373 /* Read device id register, main clock frequency register and fill in driver info structure */
374 static int at91sam7_read_part_info(struct flash_bank
*bank
)
376 struct flash_bank
*t_bank
= bank
;
377 struct at91sam7_flash_bank
*at91sam7_info
;
378 struct target
*target
= t_bank
->target
;
383 uint8_t banks_num
= 0;
384 uint16_t num_nvmbits
= 0;
385 uint16_t sectors_num
= 0;
386 uint16_t pages_per_sector
= 0;
387 uint16_t page_size
= 0;
390 uint32_t base_address
= 0;
391 char *target_name_t
= "Unknown";
393 at91sam7_info
= t_bank
->driver_priv
;
395 if (at91sam7_info
->cidr
!= 0)
397 /* flash already configured, update clock and check for protected sectors */
398 struct flash_bank
*fb
= bank
;
403 /* re-calculate master clock frequency */
404 at91sam7_read_clock_info(t_bank
);
407 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
409 /* check protect state */
410 at91sam7_protect_check(t_bank
);
419 /* Read and parse chip identification register */
420 target_read_u32(target
, DBGU_CIDR
, &cidr
);
423 LOG_WARNING("Cannot identify target as an AT91SAM");
424 return ERROR_FLASH_OPERATION_FAILED
;
427 if (at91sam7_info
->flash_autodetection
== 0)
429 /* banks and sectors are already created, based on data from input file */
430 struct flash_bank
*fb
= bank
;
434 at91sam7_info
= t_bank
->driver_priv
;
436 at91sam7_info
->cidr
= cidr
;
437 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
438 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
439 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
440 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
441 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
442 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
443 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
444 at91sam7_info
->cidr_version
= cidr
&0x001F;
446 /* calculate master clock frequency */
447 at91sam7_read_clock_info(t_bank
);
450 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
452 /* check protect state */
453 at91sam7_protect_check(t_bank
);
462 arch
= (cidr
>> 20)&0x00FF;
464 /* check flash size */
465 switch ((cidr
>> 8)&0x000F)
470 case FLASH_SIZE_16KB
:
473 pages_per_sector
= 32;
475 base_address
= 0x00100000;
479 target_name_t
= "AT91SAM7S161/16";
483 case FLASH_SIZE_32KB
:
486 pages_per_sector
= 32;
488 base_address
= 0x00100000;
492 target_name_t
= "AT91SAM7S321/32";
497 target_name_t
= "AT91SAM7SE32";
501 case FLASH_SIZE_64KB
:
504 pages_per_sector
= 32;
506 base_address
= 0x00100000;
510 target_name_t
= "AT91SAM7S64";
514 case FLASH_SIZE_128KB
:
517 pages_per_sector
= 64;
519 base_address
= 0x00100000;
523 target_name_t
= "AT91SAM7S128";
528 target_name_t
= "AT91SAM7XC128";
533 target_name_t
= "AT91SAM7SE128";
538 target_name_t
= "AT91SAM7X128";
542 case FLASH_SIZE_256KB
:
545 pages_per_sector
= 64;
547 base_address
= 0x00100000;
551 target_name_t
= "AT91SAM7A3";
556 target_name_t
= "AT91SAM7S256";
561 target_name_t
= "AT91SAM7XC256";
566 target_name_t
= "AT91SAM7SE256";
571 target_name_t
= "AT91SAM7X256";
575 case FLASH_SIZE_512KB
:
578 pages_per_sector
= 64;
580 base_address
= 0x00100000;
584 target_name_t
= "AT91SAM7S512";
589 target_name_t
= "AT91SAM7XC512";
594 target_name_t
= "AT91SAM7SE512";
599 target_name_t
= "AT91SAM7X512";
603 case FLASH_SIZE_1024KB
:
606 case FLASH_SIZE_2048KB
:
610 if (strcmp(target_name_t
, "Unknown") == 0)
612 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
613 return ERROR_FLASH_OPERATION_FAILED
;
616 ext_freq
= at91sam7_info
->ext_freq
;
618 /* calculate bank size */
619 bank_size
= sectors_num
* pages_per_sector
* page_size
;
621 for (bnk
= 0; bnk
< banks_num
; bnk
++)
625 /* create a new flash bank element */
626 struct flash_bank
*fb
= malloc(sizeof(struct flash_bank
));
628 fb
->driver
= bank
->driver
;
629 fb
->driver_priv
= malloc(sizeof(struct at91sam7_flash_bank
));
632 /* link created bank in 'flash_banks' list and redirect t_bank */
637 t_bank
->bank_number
= bnk
;
638 t_bank
->base
= base_address
+ bnk
* bank_size
;
639 t_bank
->size
= bank_size
;
640 t_bank
->chip_width
= 0;
641 t_bank
->bus_width
= 4;
642 t_bank
->num_sectors
= sectors_num
;
644 /* allocate sectors */
645 t_bank
->sectors
= malloc(sectors_num
* sizeof(struct flash_sector
));
646 for (sec
= 0; sec
< sectors_num
; sec
++)
648 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
649 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
650 t_bank
->sectors
[sec
].is_erased
= -1;
651 t_bank
->sectors
[sec
].is_protected
= -1;
654 at91sam7_info
= t_bank
->driver_priv
;
656 at91sam7_info
->cidr
= cidr
;
657 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
658 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
659 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
660 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
661 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
662 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
663 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
664 at91sam7_info
->cidr_version
= cidr
&0x001F;
666 at91sam7_info
->target_name
= target_name_t
;
667 at91sam7_info
->flashmode
= 0;
668 at91sam7_info
->ext_freq
= ext_freq
;
669 at91sam7_info
->num_nvmbits
= num_nvmbits
;
670 at91sam7_info
->num_nvmbits_on
= 0;
671 at91sam7_info
->pagesize
= page_size
;
672 at91sam7_info
->pages_per_sector
= pages_per_sector
;
674 /* calculate master clock frequency */
675 at91sam7_read_clock_info(t_bank
);
678 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
680 /* check protect state */
681 at91sam7_protect_check(t_bank
);
684 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info
->cidr_nvptyp
, at91sam7_info
->cidr_arch
);
689 static int at91sam7_erase_check(struct flash_bank
*bank
)
691 struct target
*target
= bank
->target
;
699 if (bank
->target
->state
!= TARGET_HALTED
)
701 LOG_ERROR("Target not halted");
702 return ERROR_TARGET_NOT_HALTED
;
705 /* Configure the flash controller timing */
706 at91sam7_read_clock_info(bank
);
707 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
710 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++)
712 retval
= target_blank_check_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
,
713 bank
->sectors
[nSector
].size
, &blank
);
714 if (retval
!= ERROR_OK
)
720 bank
->sectors
[nSector
].is_erased
= 1;
722 bank
->sectors
[nSector
].is_erased
= 0;
730 LOG_USER("Running slow fallback erase check - add working memory");
732 buffer
= malloc(bank
->sectors
[0].size
);
733 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++)
735 bank
->sectors
[nSector
].is_erased
= 1;
736 retval
= target_read_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
, 4,
737 bank
->sectors
[nSector
].size
/4, buffer
);
738 if (retval
!= ERROR_OK
)
741 for (nByte
= 0; nByte
< bank
->sectors
[nSector
].size
; nByte
++)
743 if (buffer
[nByte
] != 0xFF)
745 bank
->sectors
[nSector
].is_erased
= 0;
755 static int at91sam7_protect_check(struct flash_bank
*bank
)
757 uint8_t lock_pos
, gpnvm_pos
;
760 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
762 if (at91sam7_info
->cidr
== 0)
764 return ERROR_FLASH_BANK_NOT_PROBED
;
766 if (bank
->target
->state
!= TARGET_HALTED
)
768 LOG_ERROR("Target not halted");
769 return ERROR_TARGET_NOT_HALTED
;
772 status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
);
773 at91sam7_info
->lockbits
= (status
>> 16);
775 at91sam7_info
->num_lockbits_on
= 0;
776 for (lock_pos
= 0; lock_pos
< bank
->num_sectors
; lock_pos
++)
778 if (((status
>> (16 + lock_pos
))&(0x0001)) == 1)
780 at91sam7_info
->num_lockbits_on
++;
781 bank
->sectors
[lock_pos
].is_protected
= 1;
784 bank
->sectors
[lock_pos
].is_protected
= 0;
787 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
788 status
= at91sam7_get_flash_status(bank
->target
, 0);
790 at91sam7_info
->securitybit
= (status
>> 4)&0x01;
791 at91sam7_info
->nvmbits
= (status
>> 8)&0xFF;
793 at91sam7_info
->num_nvmbits_on
= 0;
794 for (gpnvm_pos
= 0; gpnvm_pos
< at91sam7_info
->num_nvmbits
; gpnvm_pos
++)
796 if (((status
>> (8 + gpnvm_pos
))&(0x01)) == 1)
798 at91sam7_info
->num_nvmbits_on
++;
805 FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command
)
807 struct flash_bank
*t_bank
= bank
;
808 struct at91sam7_flash_bank
*at91sam7_info
;
809 struct target
*target
= t_bank
->target
;
811 uint32_t base_address
;
813 uint32_t ext_freq
= 0;
820 uint16_t pages_per_sector
;
822 uint16_t num_nvmbits
;
828 at91sam7_info
= malloc(sizeof(struct at91sam7_flash_bank
));
829 t_bank
->driver_priv
= at91sam7_info
;
831 /* part wasn't probed for info yet */
832 at91sam7_info
->cidr
= 0;
833 at91sam7_info
->flashmode
= 0;
834 at91sam7_info
->ext_freq
= 0;
835 at91sam7_info
->flash_autodetection
= 0;
839 at91sam7_info
->flash_autodetection
= 1;
843 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], base_address
);
845 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[3], chip_width
);
846 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[4], bus_width
);
848 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[8], banks_num
);
849 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[9], num_sectors
);
850 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[10], pages_per_sector
);
851 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[11], page_size
);
852 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[12], num_nvmbits
);
854 if (CMD_ARGC
== 14) {
856 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[13], freq
);
857 ext_freq
= freq
* 1000;
858 at91sam7_info
->ext_freq
= ext_freq
;
861 if ((bus_width
== 0) || (banks_num
== 0) || (num_sectors
== 0) ||
862 (pages_per_sector
== 0) || (page_size
== 0) || (num_nvmbits
== 0))
864 at91sam7_info
->flash_autodetection
= 1;
868 target_name_t
= calloc(strlen(CMD_ARGV
[7]) + 1, sizeof(char));
869 strcpy(target_name_t
, CMD_ARGV
[7]);
871 /* calculate bank size */
872 bank_size
= num_sectors
* pages_per_sector
* page_size
;
874 for (bnk
= 0; bnk
< banks_num
; bnk
++)
878 /* create a new bank element */
879 struct flash_bank
*fb
= malloc(sizeof(struct flash_bank
));
881 fb
->driver
= bank
->driver
;
882 fb
->driver_priv
= malloc(sizeof(struct at91sam7_flash_bank
));
885 /* link created bank in 'flash_banks' list and redirect t_bank */
890 t_bank
->bank_number
= bnk
;
891 t_bank
->base
= base_address
+ bnk
* bank_size
;
892 t_bank
->size
= bank_size
;
893 t_bank
->chip_width
= chip_width
;
894 t_bank
->bus_width
= bus_width
;
895 t_bank
->num_sectors
= num_sectors
;
897 /* allocate sectors */
898 t_bank
->sectors
= malloc(num_sectors
* sizeof(struct flash_sector
));
899 for (sec
= 0; sec
< num_sectors
; sec
++)
901 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
902 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
903 t_bank
->sectors
[sec
].is_erased
= -1;
904 t_bank
->sectors
[sec
].is_protected
= -1;
907 at91sam7_info
= t_bank
->driver_priv
;
909 at91sam7_info
->target_name
= target_name_t
;
910 at91sam7_info
->flashmode
= 0;
911 at91sam7_info
->ext_freq
= ext_freq
;
912 at91sam7_info
->num_nvmbits
= num_nvmbits
;
913 at91sam7_info
->num_nvmbits_on
= 0;
914 at91sam7_info
->pagesize
= page_size
;
915 at91sam7_info
->pages_per_sector
= pages_per_sector
;
921 static int at91sam7_erase(struct flash_bank
*bank
, int first
, int last
)
923 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
925 uint32_t nbytes
, pos
;
929 if (at91sam7_info
->cidr
== 0)
931 return ERROR_FLASH_BANK_NOT_PROBED
;
934 if (bank
->target
->state
!= TARGET_HALTED
)
936 LOG_ERROR("Target not halted");
937 return ERROR_TARGET_NOT_HALTED
;
940 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
942 return ERROR_FLASH_SECTOR_INVALID
;
946 if ((first
== 0) && (last
== (bank
->num_sectors
-1)))
951 /* Configure the flash controller timing */
952 at91sam7_read_clock_info(bank
);
953 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
957 if (at91sam7_flash_command(bank
, EA
, 0) != ERROR_OK
)
959 return ERROR_FLASH_OPERATION_FAILED
;
964 /* allocate and clean buffer */
965 nbytes
= (last
- first
+ 1) * bank
->sectors
[first
].size
;
966 buffer
= malloc(nbytes
* sizeof(uint8_t));
967 for (pos
= 0; pos
< nbytes
; pos
++)
972 if (at91sam7_write(bank
, buffer
, bank
->sectors
[first
].offset
, nbytes
) != ERROR_OK
)
974 return ERROR_FLASH_OPERATION_FAILED
;
980 /* mark erased sectors */
981 for (sec
= first
; sec
<= last
; sec
++)
983 bank
->sectors
[sec
].is_erased
= 1;
989 static int at91sam7_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
995 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
997 if (at91sam7_info
->cidr
== 0)
999 return ERROR_FLASH_BANK_NOT_PROBED
;
1002 if (bank
->target
->state
!= TARGET_HALTED
)
1004 LOG_ERROR("Target not halted");
1005 return ERROR_TARGET_NOT_HALTED
;
1008 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
1010 return ERROR_FLASH_SECTOR_INVALID
;
1013 /* Configure the flash controller timing */
1014 at91sam7_read_clock_info(bank
);
1015 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
1017 for (sector
= first
; sector
<= last
; sector
++)
1024 /* if we lock a page from one sector then entire sector will be locked, also,
1025 * if we unlock a page from a locked sector, entire sector will be unlocked */
1026 pagen
= sector
* at91sam7_info
->pages_per_sector
;
1028 if (at91sam7_flash_command(bank
, cmd
, pagen
) != ERROR_OK
)
1030 return ERROR_FLASH_OPERATION_FAILED
;
1034 at91sam7_protect_check(bank
);
1039 static int at91sam7_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1042 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
1043 struct target
*target
= bank
->target
;
1044 uint32_t dst_min_alignment
, wcount
, bytes_remaining
= count
;
1045 uint32_t first_page
, last_page
, pagen
, buffer_pos
;
1047 if (at91sam7_info
->cidr
== 0)
1049 return ERROR_FLASH_BANK_NOT_PROBED
;
1052 if (bank
->target
->state
!= TARGET_HALTED
)
1054 LOG_ERROR("Target not halted");
1055 return ERROR_TARGET_NOT_HALTED
;
1058 if (offset
+ count
> bank
->size
)
1059 return ERROR_FLASH_DST_OUT_OF_BANK
;
1061 dst_min_alignment
= at91sam7_info
->pagesize
;
1063 if (offset
% dst_min_alignment
)
1065 LOG_WARNING("offset 0x%" PRIx32
" breaks required alignment 0x%" PRIx32
"", offset
, dst_min_alignment
);
1066 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
1069 if (at91sam7_info
->cidr_arch
== 0)
1070 return ERROR_FLASH_BANK_NOT_PROBED
;
1072 first_page
= offset
/dst_min_alignment
;
1073 last_page
= DIV_ROUND_UP(offset
+ count
, dst_min_alignment
);
1075 LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page
, (int)last_page
, (int)count
);
1077 /* Configure the flash controller timing */
1078 at91sam7_read_clock_info(bank
);
1079 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
1081 for (pagen
= first_page
; pagen
< last_page
; pagen
++)
1083 if (bytes_remaining
< dst_min_alignment
)
1084 count
= bytes_remaining
;
1086 count
= dst_min_alignment
;
1087 bytes_remaining
-= count
;
1089 /* Write one block to the PageWriteBuffer */
1090 buffer_pos
= (pagen
-first_page
)*dst_min_alignment
;
1091 wcount
= DIV_ROUND_UP(count
,4);
1092 if ((retval
= target_write_memory(target
, bank
->base
+ pagen
*dst_min_alignment
, 4, wcount
, buffer
+ buffer_pos
)) != ERROR_OK
)
1097 /* Send Write Page command to Flash Controller */
1098 if (at91sam7_flash_command(bank
, WP
, pagen
) != ERROR_OK
)
1100 return ERROR_FLASH_OPERATION_FAILED
;
1102 LOG_DEBUG("Write flash bank:%i page number:%" PRIi32
"", bank
->bank_number
, pagen
);
1108 static int at91sam7_probe(struct flash_bank
*bank
)
1110 /* we can't probe on an at91sam7
1111 * if this is an at91sam7, it has the configured flash */
1114 if (bank
->target
->state
!= TARGET_HALTED
)
1116 LOG_ERROR("Target not halted");
1117 return ERROR_TARGET_NOT_HALTED
;
1120 retval
= at91sam7_read_part_info(bank
);
1121 if (retval
!= ERROR_OK
)
1127 static int get_at91sam7_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1130 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
1132 if (at91sam7_info
->cidr
== 0)
1134 return ERROR_FLASH_BANK_NOT_PROBED
;
1137 printed
= snprintf(buf
, buf_size
,
1138 "\n at91sam7 driver information: Chip is %s\n",
1139 at91sam7_info
->target_name
);
1142 buf_size
-= printed
;
1144 printed
= snprintf(buf
,
1146 " Cidr: 0x%8.8" PRIx32
" | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32
"\n",
1147 at91sam7_info
->cidr
,
1148 at91sam7_info
->cidr_arch
,
1149 EPROC
[at91sam7_info
->cidr_eproc
],
1150 at91sam7_info
->cidr_version
,
1154 buf_size
-= printed
;
1156 printed
= snprintf(buf
, buf_size
,
1157 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1158 (unsigned)(at91sam7_info
->mck_freq
/ 1000), (unsigned)(at91sam7_info
->ext_freq
/ 1000));
1161 buf_size
-= printed
;
1163 printed
= snprintf(buf
, buf_size
,
1164 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1165 at91sam7_info
->pagesize
, bank
->num_sectors
, at91sam7_info
->num_lockbits_on
,
1166 at91sam7_info
->lockbits
, at91sam7_info
->pages_per_sector
*at91sam7_info
->num_lockbits_on
);
1169 buf_size
-= printed
;
1171 printed
= snprintf(buf
, buf_size
,
1172 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1173 at91sam7_info
->securitybit
, at91sam7_info
->num_nvmbits
,
1174 at91sam7_info
->num_nvmbits_on
, at91sam7_info
->nvmbits
);
1177 buf_size
-= printed
;
1183 * On AT91SAM7S: When the gpnvm bits are set with
1184 * > at91sam7 gpnvm bitnr set
1185 * the changes are not visible in the flash controller status register MC_FSR
1186 * until the processor has been reset.
1187 * On the Olimex board this requires a power cycle.
1188 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1189 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1190 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1192 COMMAND_HANDLER(at91sam7_handle_gpnvm_command
)
1194 struct flash_bank
*bank
;
1198 struct at91sam7_flash_bank
*at91sam7_info
;
1203 command_print(CMD_CTX
, "at91sam7 gpnvm <bit> <set | clear>");
1207 bank
= get_flash_bank_by_num_noprobe(0);
1210 return ERROR_FLASH_BANK_INVALID
;
1212 if (strcmp(bank
->driver
->name
, "at91sam7"))
1214 command_print(CMD_CTX
, "not an at91sam7 flash bank '%s'", CMD_ARGV
[0]);
1215 return ERROR_FLASH_BANK_INVALID
;
1217 if (bank
->target
->state
!= TARGET_HALTED
)
1219 LOG_ERROR("target has to be halted to perform flash operation");
1220 return ERROR_TARGET_NOT_HALTED
;
1223 if (strcmp(CMD_ARGV
[1], "set") == 0)
1227 else if (strcmp(CMD_ARGV
[1], "clear") == 0)
1233 return ERROR_COMMAND_SYNTAX_ERROR
;
1236 at91sam7_info
= bank
->driver_priv
;
1237 if (at91sam7_info
->cidr
== 0)
1239 retval
= at91sam7_read_part_info(bank
);
1240 if (retval
!= ERROR_OK
)
1246 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], bit
);
1247 if ((bit
< 0) || (bit
>= at91sam7_info
->num_nvmbits
))
1249 command_print(CMD_CTX
, "gpnvm bit '#%s' is out of bounds for target %s", CMD_ARGV
[0], at91sam7_info
->target_name
);
1253 /* Configure the flash controller timing */
1254 at91sam7_read_clock_info(bank
);
1255 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
1257 if (at91sam7_flash_command(bank
, flashcmd
, bit
) != ERROR_OK
)
1259 return ERROR_FLASH_OPERATION_FAILED
;
1262 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1263 status
= at91sam7_get_flash_status(bank
->target
, 0);
1264 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32
" \n", flashcmd
, bit
, status
);
1266 /* check protect state */
1267 at91sam7_protect_check(bank
);
1272 static const struct command_registration at91sam7_exec_command_handlers
[] = {
1275 .handler
= at91sam7_handle_gpnvm_command
,
1276 .mode
= COMMAND_EXEC
,
1277 .help
= "set or clear one General Purpose Non-Volatile Memory "
1279 .usage
= "bitnum ('set'|'clear')",
1281 COMMAND_REGISTRATION_DONE
1283 static const struct command_registration at91sam7_command_handlers
[] = {
1286 .mode
= COMMAND_ANY
,
1287 .help
= "at91sam7 flash command group",
1288 .chain
= at91sam7_exec_command_handlers
,
1290 COMMAND_REGISTRATION_DONE
1293 struct flash_driver at91sam7_flash
= {
1295 .commands
= at91sam7_command_handlers
,
1296 .flash_bank_command
= at91sam7_flash_bank_command
,
1297 .erase
= at91sam7_erase
,
1298 .protect
= at91sam7_protect
,
1299 .write
= at91sam7_write
,
1300 .read
= default_flash_read
,
1301 .probe
= at91sam7_probe
,
1302 .auto_probe
= at91sam7_probe
,
1303 .erase_check
= at91sam7_erase_check
,
1304 .protect_check
= at91sam7_protect_check
,
1305 .info
= get_at91sam7_info
,
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