1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
15 * GNU General public License for more details. *
17 * You should have received a copy of the GNU General public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ****************************************************************************/
23 /***************************************************************************
25 * New flash setup command:
27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
28 * [<chip_type> <banks>
29 * <sectors_per_bank> <pages_per_sector>
30 * <page_size> <num_nvmbits>
33 * <ext_freq_khz> - MUST be used if clock is from external source,
34 * CAN be used if main oscillator frequency is known (recommended)
36 * ==== RECOMMENDED (covers clock speed) ============
37 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
38 * (if auto-detect fails; provides clock spec)
39 * flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
40 * (auto-detect everything except the clock)
41 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
42 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
43 * (if auto-detect fails)
44 * flash bank at91sam7 0 0 0 0 $_TARGETNAME
45 * (old style, auto-detect everything)
46 ****************************************************************************/
54 #include <helper/binarybuffer.h>
56 static int at91sam7_protect_check(struct flash_bank
*bank
);
57 static int at91sam7_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
);
59 static uint32_t at91sam7_get_flash_status(struct target
*target
, int bank_number
);
60 static void at91sam7_set_flash_mode(struct flash_bank
*bank
, int mode
);
61 static uint32_t at91sam7_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
);
62 static int at91sam7_flash_command(struct flash_bank
*bank
, uint8_t cmd
, uint16_t pagen
);
64 static uint32_t MC_FMR
[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
65 static uint32_t MC_FCR
[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
66 static uint32_t MC_FSR
[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
68 static char * EPROC
[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
71 static long SRAMSIZ
[16] = {
92 static uint32_t at91sam7_get_flash_status(struct target
*target
, int bank_number
)
95 target_read_u32(target
, MC_FSR
[bank_number
], &fsr
);
100 /* Read clock configuration and set at91sam7_info->mck_freq */
101 static void at91sam7_read_clock_info(struct flash_bank
*bank
)
103 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
104 struct target
*target
= bank
->target
;
105 uint32_t mckr
, mcfr
, pllr
, mor
;
106 unsigned long tmp
= 0, mainfreq
;
108 /* Read Clock Generator Main Oscillator Register */
109 target_read_u32(target
, CKGR_MOR
, &mor
);
110 /* Read Clock Generator Main Clock Frequency Register */
111 target_read_u32(target
, CKGR_MCFR
, &mcfr
);
112 /* Read Master Clock Register*/
113 target_read_u32(target
, PMC_MCKR
, &mckr
);
114 /* Read Clock Generator PLL Register */
115 target_read_u32(target
, CKGR_PLLR
, &pllr
);
117 at91sam7_info
->mck_valid
= 0;
118 at91sam7_info
->mck_freq
= 0;
119 switch (mckr
& PMC_MCKR_CSS
)
121 case 0: /* Slow Clock */
122 at91sam7_info
->mck_valid
= 1;
126 case 1: /* Main Clock */
127 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
128 (at91sam7_info
->ext_freq
== 0))
130 at91sam7_info
->mck_valid
= 1;
131 tmp
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
133 else if (at91sam7_info
->ext_freq
!= 0)
135 at91sam7_info
->mck_valid
= 1;
136 tmp
= at91sam7_info
->ext_freq
;
140 case 2: /* Reserved */
143 case 3: /* PLL Clock */
144 if ((mcfr
& CKGR_MCFR_MAINRDY
) &&
145 (at91sam7_info
->ext_freq
== 0))
147 target_read_u32(target
, CKGR_PLLR
, &pllr
);
148 if (!(pllr
& CKGR_PLLR_DIV
))
150 at91sam7_info
->mck_valid
= 1;
151 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
152 /* Integer arithmetic should have sufficient precision
153 * as long as PLL is properly configured. */
154 tmp
= mainfreq
/ (pllr
& CKGR_PLLR_DIV
)*
155 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
157 else if ((at91sam7_info
->ext_freq
!= 0) &&
158 ((pllr
&CKGR_PLLR_DIV
) != 0))
160 at91sam7_info
->mck_valid
= 1;
161 tmp
= at91sam7_info
->ext_freq
/ (pllr
&CKGR_PLLR_DIV
)*
162 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
167 /* Prescaler adjust */
168 if ((((mckr
& PMC_MCKR_PRES
) >> 2) == 7) || (tmp
== 0))
170 at91sam7_info
->mck_valid
= 0;
171 at91sam7_info
->mck_freq
= 0;
173 else if (((mckr
& PMC_MCKR_PRES
) >> 2) != 0)
174 at91sam7_info
->mck_freq
= tmp
>> ((mckr
& PMC_MCKR_PRES
) >> 2);
176 at91sam7_info
->mck_freq
= tmp
;
179 /* Setup the timimg registers for nvbits or normal flash */
180 static void at91sam7_set_flash_mode(struct flash_bank
*bank
, int mode
)
182 uint32_t fmr
, fmcn
= 0, fws
= 0;
183 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
184 struct target
*target
= bank
->target
;
186 if (mode
&& (mode
!= at91sam7_info
->flashmode
))
188 /* Always round up (ceil) */
189 if (mode
== FMR_TIMING_NVBITS
)
191 if (at91sam7_info
->cidr_arch
== 0x60)
193 /* AT91SAM7A3 uses master clocks in 100 ns */
194 fmcn
= (at91sam7_info
->mck_freq
/10000000ul) + 1;
198 /* master clocks in 1uS for ARCH 0x7 types */
199 fmcn
= (at91sam7_info
->mck_freq
/1000000ul) + 1;
202 else if (mode
== FMR_TIMING_FLASH
)
204 /* main clocks in 1.5uS */
205 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+
206 (at91sam7_info
->mck_freq
/2000000ul) + 1;
209 /* hard overclocking */
213 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
214 if (at91sam7_info
->mck_freq
<= 33333ul)
216 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
217 if (at91sam7_info
->mck_freq
> 30000000ul)
220 LOG_DEBUG("fmcn[%i]: %i", bank
->bank_number
, (int)(fmcn
));
221 fmr
= fmcn
<< 16 | fws
<< 8;
222 target_write_u32(target
, MC_FMR
[bank
->bank_number
], fmr
);
225 at91sam7_info
->flashmode
= mode
;
228 static uint32_t at91sam7_wait_status_busy(struct flash_bank
*bank
, uint32_t waitbits
, int timeout
)
232 while ((!((status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
)) & waitbits
)) && (timeout
-- > 0))
234 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", (int)bank
->bank_number
, status
);
238 LOG_DEBUG("status[%i]: 0x%" PRIx32
"", bank
->bank_number
, status
);
242 LOG_ERROR("status register: 0x%" PRIx32
"", status
);
244 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
246 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
248 LOG_ERROR("Security Bit Set, Operation Abort");
254 /* Send one command to the AT91SAM flash controller */
255 static int at91sam7_flash_command(struct flash_bank
*bank
, uint8_t cmd
, uint16_t pagen
)
258 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
259 struct target
*target
= bank
->target
;
261 fcr
= (0x5A << 24) | ((pagen
&0x3FF) << 8) | cmd
;
262 target_write_u32(target
, MC_FCR
[bank
->bank_number
], fcr
);
263 LOG_DEBUG("Flash command: 0x%" PRIx32
", flash bank: %i, page number: %u", fcr
, bank
->bank_number
+ 1, pagen
);
265 if ((at91sam7_info
->cidr_arch
== 0x60) && ((cmd
== SLB
) | (cmd
== CLB
)))
267 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
268 if (at91sam7_wait_status_busy(bank
, MC_FSR_EOL
, 10)&0x0C)
270 return ERROR_FLASH_OPERATION_FAILED
;
275 if (at91sam7_wait_status_busy(bank
, MC_FSR_FRDY
, 10)&0x0C)
277 return ERROR_FLASH_OPERATION_FAILED
;
283 /* Read device id register, main clock frequency register and fill in driver info structure */
284 static int at91sam7_read_part_info(struct flash_bank
*bank
)
286 struct flash_bank
*t_bank
= bank
;
287 struct at91sam7_flash_bank
*at91sam7_info
;
288 struct target
*target
= t_bank
->target
;
293 uint8_t banks_num
= 0;
294 uint16_t num_nvmbits
= 0;
295 uint16_t sectors_num
= 0;
296 uint16_t pages_per_sector
= 0;
297 uint16_t page_size
= 0;
300 uint32_t base_address
= 0;
301 char *target_name
= "Unknown";
303 at91sam7_info
= t_bank
->driver_priv
;
305 if (at91sam7_info
->cidr
!= 0)
307 /* flash already configured, update clock and check for protected sectors */
308 struct flash_bank
*fb
= bank
;
313 /* re-calculate master clock frequency */
314 at91sam7_read_clock_info(t_bank
);
317 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
319 /* check protect state */
320 at91sam7_protect_check(t_bank
);
329 /* Read and parse chip identification register */
330 target_read_u32(target
, DBGU_CIDR
, &cidr
);
333 LOG_WARNING("Cannot identify target as an AT91SAM");
334 return ERROR_FLASH_OPERATION_FAILED
;
337 if (at91sam7_info
->flash_autodetection
== 0)
339 /* banks and sectors are already created, based on data from input file */
340 struct flash_bank
*fb
= bank
;
344 at91sam7_info
= t_bank
->driver_priv
;
346 at91sam7_info
->cidr
= cidr
;
347 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
348 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
349 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
350 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
351 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
352 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
353 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
354 at91sam7_info
->cidr_version
= cidr
&0x001F;
356 /* calculate master clock frequency */
357 at91sam7_read_clock_info(t_bank
);
360 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
362 /* check protect state */
363 at91sam7_protect_check(t_bank
);
372 arch
= (cidr
>> 20)&0x00FF;
374 /* check flash size */
375 switch ((cidr
>> 8)&0x000F)
380 case FLASH_SIZE_16KB
:
383 pages_per_sector
= 32;
385 base_address
= 0x00100000;
389 target_name
= "AT91SAM7S161/16";
393 case FLASH_SIZE_32KB
:
396 pages_per_sector
= 32;
398 base_address
= 0x00100000;
402 target_name
= "AT91SAM7S321/32";
407 target_name
= "AT91SAM7SE32";
411 case FLASH_SIZE_64KB
:
414 pages_per_sector
= 32;
416 base_address
= 0x00100000;
420 target_name
= "AT91SAM7S64";
424 case FLASH_SIZE_128KB
:
427 pages_per_sector
= 64;
429 base_address
= 0x00100000;
433 target_name
= "AT91SAM7S128";
438 target_name
= "AT91SAM7XC128";
443 target_name
= "AT91SAM7SE128";
448 target_name
= "AT91SAM7X128";
452 case FLASH_SIZE_256KB
:
455 pages_per_sector
= 64;
457 base_address
= 0x00100000;
461 target_name
= "AT91SAM7A3";
466 target_name
= "AT91SAM7S256";
471 target_name
= "AT91SAM7XC256";
476 target_name
= "AT91SAM7SE256";
481 target_name
= "AT91SAM7X256";
485 case FLASH_SIZE_512KB
:
488 pages_per_sector
= 64;
490 base_address
= 0x00100000;
494 target_name
= "AT91SAM7S512";
499 target_name
= "AT91SAM7XC512";
504 target_name
= "AT91SAM7SE512";
509 target_name
= "AT91SAM7X512";
513 case FLASH_SIZE_1024KB
:
516 case FLASH_SIZE_2048KB
:
520 if (strcmp(target_name
, "Unknown") == 0)
522 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
523 return ERROR_FLASH_OPERATION_FAILED
;
526 ext_freq
= at91sam7_info
->ext_freq
;
528 /* calculate bank size */
529 bank_size
= sectors_num
* pages_per_sector
* page_size
;
531 for (bnk
= 0; bnk
< banks_num
; bnk
++)
535 /* create a new flash bank element */
536 struct flash_bank
*fb
= malloc(sizeof(struct flash_bank
));
538 fb
->driver
= bank
->driver
;
539 fb
->driver_priv
= malloc(sizeof(struct at91sam7_flash_bank
));
542 /* link created bank in 'flash_banks' list and redirect t_bank */
547 t_bank
->bank_number
= bnk
;
548 t_bank
->base
= base_address
+ bnk
* bank_size
;
549 t_bank
->size
= bank_size
;
550 t_bank
->chip_width
= 0;
551 t_bank
->bus_width
= 4;
552 t_bank
->num_sectors
= sectors_num
;
554 /* allocate sectors */
555 t_bank
->sectors
= malloc(sectors_num
* sizeof(struct flash_sector
));
556 for (sec
= 0; sec
< sectors_num
; sec
++)
558 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
559 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
560 t_bank
->sectors
[sec
].is_erased
= -1;
561 t_bank
->sectors
[sec
].is_protected
= -1;
564 at91sam7_info
= t_bank
->driver_priv
;
566 at91sam7_info
->cidr
= cidr
;
567 at91sam7_info
->cidr_ext
= (cidr
>> 31)&0x0001;
568 at91sam7_info
->cidr_nvptyp
= (cidr
>> 28)&0x0007;
569 at91sam7_info
->cidr_arch
= (cidr
>> 20)&0x00FF;
570 at91sam7_info
->cidr_sramsiz
= (cidr
>> 16)&0x000F;
571 at91sam7_info
->cidr_nvpsiz2
= (cidr
>> 12)&0x000F;
572 at91sam7_info
->cidr_nvpsiz
= (cidr
>> 8)&0x000F;
573 at91sam7_info
->cidr_eproc
= (cidr
>> 5)&0x0007;
574 at91sam7_info
->cidr_version
= cidr
&0x001F;
576 at91sam7_info
->target_name
= target_name
;
577 at91sam7_info
->flashmode
= 0;
578 at91sam7_info
->ext_freq
= ext_freq
;
579 at91sam7_info
->num_nvmbits
= num_nvmbits
;
580 at91sam7_info
->num_nvmbits_on
= 0;
581 at91sam7_info
->pagesize
= page_size
;
582 at91sam7_info
->pages_per_sector
= pages_per_sector
;
584 /* calculate master clock frequency */
585 at91sam7_read_clock_info(t_bank
);
588 at91sam7_set_flash_mode(t_bank
, FMR_TIMING_NONE
);
590 /* check protect state */
591 at91sam7_protect_check(t_bank
);
594 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info
->cidr_nvptyp
, at91sam7_info
->cidr_arch
);
599 static int at91sam7_erase_check(struct flash_bank
*bank
)
601 struct target
*target
= bank
->target
;
609 if (bank
->target
->state
!= TARGET_HALTED
)
611 LOG_ERROR("Target not halted");
612 return ERROR_TARGET_NOT_HALTED
;
615 /* Configure the flash controller timing */
616 at91sam7_read_clock_info(bank
);
617 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
620 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++)
622 retval
= target_blank_check_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
,
623 bank
->sectors
[nSector
].size
, &blank
);
624 if (retval
!= ERROR_OK
)
630 bank
->sectors
[nSector
].is_erased
= 1;
632 bank
->sectors
[nSector
].is_erased
= 0;
640 LOG_USER("Running slow fallback erase check - add working memory");
642 buffer
= malloc(bank
->sectors
[0].size
);
643 for (nSector
= 0; nSector
< bank
->num_sectors
; nSector
++)
645 bank
->sectors
[nSector
].is_erased
= 1;
646 retval
= target_read_memory(target
, bank
->base
+ bank
->sectors
[nSector
].offset
, 4,
647 bank
->sectors
[nSector
].size
/4, buffer
);
648 if (retval
!= ERROR_OK
)
651 for (nByte
= 0; nByte
< bank
->sectors
[nSector
].size
; nByte
++)
653 if (buffer
[nByte
] != 0xFF)
655 bank
->sectors
[nSector
].is_erased
= 0;
665 static int at91sam7_protect_check(struct flash_bank
*bank
)
667 uint8_t lock_pos
, gpnvm_pos
;
670 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
672 if (at91sam7_info
->cidr
== 0)
674 return ERROR_FLASH_BANK_NOT_PROBED
;
676 if (bank
->target
->state
!= TARGET_HALTED
)
678 LOG_ERROR("Target not halted");
679 return ERROR_TARGET_NOT_HALTED
;
682 status
= at91sam7_get_flash_status(bank
->target
, bank
->bank_number
);
683 at91sam7_info
->lockbits
= (status
>> 16);
685 at91sam7_info
->num_lockbits_on
= 0;
686 for (lock_pos
= 0; lock_pos
< bank
->num_sectors
; lock_pos
++)
688 if (((status
>> (16 + lock_pos
))&(0x0001)) == 1)
690 at91sam7_info
->num_lockbits_on
++;
691 bank
->sectors
[lock_pos
].is_protected
= 1;
694 bank
->sectors
[lock_pos
].is_protected
= 0;
697 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
698 status
= at91sam7_get_flash_status(bank
->target
, 0);
700 at91sam7_info
->securitybit
= (status
>> 4)&0x01;
701 at91sam7_info
->nvmbits
= (status
>> 8)&0xFF;
703 at91sam7_info
->num_nvmbits_on
= 0;
704 for (gpnvm_pos
= 0; gpnvm_pos
< at91sam7_info
->num_nvmbits
; gpnvm_pos
++)
706 if (((status
>> (8 + gpnvm_pos
))&(0x01)) == 1)
708 at91sam7_info
->num_nvmbits_on
++;
715 FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command
)
717 struct flash_bank
*t_bank
= bank
;
718 struct at91sam7_flash_bank
*at91sam7_info
;
719 struct target
*target
= t_bank
->target
;
721 uint32_t base_address
;
723 uint32_t ext_freq
= 0;
730 uint16_t pages_per_sector
;
732 uint16_t num_nvmbits
;
738 at91sam7_info
= malloc(sizeof(struct at91sam7_flash_bank
));
739 t_bank
->driver_priv
= at91sam7_info
;
741 /* part wasn't probed for info yet */
742 at91sam7_info
->cidr
= 0;
743 at91sam7_info
->flashmode
= 0;
744 at91sam7_info
->ext_freq
= 0;
745 at91sam7_info
->flash_autodetection
= 0;
749 at91sam7_info
->flash_autodetection
= 1;
753 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], base_address
);
755 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[3], chip_width
);
756 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[4], bus_width
);
758 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[8], banks_num
);
759 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[9], num_sectors
);
760 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[10], pages_per_sector
);
761 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[11], page_size
);
762 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[12], num_nvmbits
);
764 if (CMD_ARGC
== 14) {
766 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[13], freq
);
767 ext_freq
= freq
* 1000;
768 at91sam7_info
->ext_freq
= ext_freq
;
771 if ((bus_width
== 0) || (banks_num
== 0) || (num_sectors
== 0) ||
772 (pages_per_sector
== 0) || (page_size
== 0) || (num_nvmbits
== 0))
774 at91sam7_info
->flash_autodetection
= 1;
778 target_name
= calloc(strlen(CMD_ARGV
[7]) + 1, sizeof(char));
779 strcpy(target_name
, CMD_ARGV
[7]);
781 /* calculate bank size */
782 bank_size
= num_sectors
* pages_per_sector
* page_size
;
784 for (bnk
= 0; bnk
< banks_num
; bnk
++)
788 /* create a new bank element */
789 struct flash_bank
*fb
= malloc(sizeof(struct flash_bank
));
791 fb
->driver
= bank
->driver
;
792 fb
->driver_priv
= malloc(sizeof(struct at91sam7_flash_bank
));
795 /* link created bank in 'flash_banks' list and redirect t_bank */
800 t_bank
->bank_number
= bnk
;
801 t_bank
->base
= base_address
+ bnk
* bank_size
;
802 t_bank
->size
= bank_size
;
803 t_bank
->chip_width
= chip_width
;
804 t_bank
->bus_width
= bus_width
;
805 t_bank
->num_sectors
= num_sectors
;
807 /* allocate sectors */
808 t_bank
->sectors
= malloc(num_sectors
* sizeof(struct flash_sector
));
809 for (sec
= 0; sec
< num_sectors
; sec
++)
811 t_bank
->sectors
[sec
].offset
= sec
* pages_per_sector
* page_size
;
812 t_bank
->sectors
[sec
].size
= pages_per_sector
* page_size
;
813 t_bank
->sectors
[sec
].is_erased
= -1;
814 t_bank
->sectors
[sec
].is_protected
= -1;
817 at91sam7_info
= t_bank
->driver_priv
;
819 at91sam7_info
->target_name
= target_name
;
820 at91sam7_info
->flashmode
= 0;
821 at91sam7_info
->ext_freq
= ext_freq
;
822 at91sam7_info
->num_nvmbits
= num_nvmbits
;
823 at91sam7_info
->num_nvmbits_on
= 0;
824 at91sam7_info
->pagesize
= page_size
;
825 at91sam7_info
->pages_per_sector
= pages_per_sector
;
831 static int at91sam7_erase(struct flash_bank
*bank
, int first
, int last
)
833 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
835 uint32_t nbytes
, pos
;
839 if (at91sam7_info
->cidr
== 0)
841 return ERROR_FLASH_BANK_NOT_PROBED
;
844 if (bank
->target
->state
!= TARGET_HALTED
)
846 LOG_ERROR("Target not halted");
847 return ERROR_TARGET_NOT_HALTED
;
850 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
852 return ERROR_FLASH_SECTOR_INVALID
;
856 if ((first
== 0) && (last
== (bank
->num_sectors
-1)))
861 /* Configure the flash controller timing */
862 at91sam7_read_clock_info(bank
);
863 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
867 if (at91sam7_flash_command(bank
, EA
, 0) != ERROR_OK
)
869 return ERROR_FLASH_OPERATION_FAILED
;
874 /* allocate and clean buffer */
875 nbytes
= (last
- first
+ 1) * bank
->sectors
[first
].size
;
876 buffer
= malloc(nbytes
* sizeof(uint8_t));
877 for (pos
= 0; pos
< nbytes
; pos
++)
882 if (at91sam7_write(bank
, buffer
, bank
->sectors
[first
].offset
, nbytes
) != ERROR_OK
)
884 return ERROR_FLASH_OPERATION_FAILED
;
890 /* mark erased sectors */
891 for (sec
= first
; sec
<= last
; sec
++)
893 bank
->sectors
[sec
].is_erased
= 1;
899 static int at91sam7_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
905 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
907 if (at91sam7_info
->cidr
== 0)
909 return ERROR_FLASH_BANK_NOT_PROBED
;
912 if (bank
->target
->state
!= TARGET_HALTED
)
914 LOG_ERROR("Target not halted");
915 return ERROR_TARGET_NOT_HALTED
;
918 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
920 return ERROR_FLASH_SECTOR_INVALID
;
923 /* Configure the flash controller timing */
924 at91sam7_read_clock_info(bank
);
925 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
927 for (sector
= first
; sector
<= last
; sector
++)
934 /* if we lock a page from one sector then entire sector will be locked, also,
935 * if we unlock a page from a locked sector, entire sector will be unlocked */
936 pagen
= sector
* at91sam7_info
->pages_per_sector
;
938 if (at91sam7_flash_command(bank
, cmd
, pagen
) != ERROR_OK
)
940 return ERROR_FLASH_OPERATION_FAILED
;
944 at91sam7_protect_check(bank
);
949 static int at91sam7_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
952 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
953 struct target
*target
= bank
->target
;
954 uint32_t dst_min_alignment
, wcount
, bytes_remaining
= count
;
955 uint32_t first_page
, last_page
, pagen
, buffer_pos
;
957 if (at91sam7_info
->cidr
== 0)
959 return ERROR_FLASH_BANK_NOT_PROBED
;
962 if (bank
->target
->state
!= TARGET_HALTED
)
964 LOG_ERROR("Target not halted");
965 return ERROR_TARGET_NOT_HALTED
;
968 if (offset
+ count
> bank
->size
)
969 return ERROR_FLASH_DST_OUT_OF_BANK
;
971 dst_min_alignment
= at91sam7_info
->pagesize
;
973 if (offset
% dst_min_alignment
)
975 LOG_WARNING("offset 0x%" PRIx32
" breaks required alignment 0x%" PRIx32
"", offset
, dst_min_alignment
);
976 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
979 if (at91sam7_info
->cidr_arch
== 0)
980 return ERROR_FLASH_BANK_NOT_PROBED
;
982 first_page
= offset
/dst_min_alignment
;
983 last_page
= DIV_ROUND_UP(offset
+ count
, dst_min_alignment
);
985 LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page
, (int)last_page
, (int)count
);
987 /* Configure the flash controller timing */
988 at91sam7_read_clock_info(bank
);
989 at91sam7_set_flash_mode(bank
, FMR_TIMING_FLASH
);
991 for (pagen
= first_page
; pagen
< last_page
; pagen
++)
993 if (bytes_remaining
< dst_min_alignment
)
994 count
= bytes_remaining
;
996 count
= dst_min_alignment
;
997 bytes_remaining
-= count
;
999 /* Write one block to the PageWriteBuffer */
1000 buffer_pos
= (pagen
-first_page
)*dst_min_alignment
;
1001 wcount
= DIV_ROUND_UP(count
,4);
1002 if ((retval
= target_write_memory(target
, bank
->base
+ pagen
*dst_min_alignment
, 4, wcount
, buffer
+ buffer_pos
)) != ERROR_OK
)
1007 /* Send Write Page command to Flash Controller */
1008 if (at91sam7_flash_command(bank
, WP
, pagen
) != ERROR_OK
)
1010 return ERROR_FLASH_OPERATION_FAILED
;
1012 LOG_DEBUG("Write flash bank:%i page number:%" PRIi32
"", bank
->bank_number
, pagen
);
1018 static int at91sam7_probe(struct flash_bank
*bank
)
1020 /* we can't probe on an at91sam7
1021 * if this is an at91sam7, it has the configured flash */
1024 if (bank
->target
->state
!= TARGET_HALTED
)
1026 LOG_ERROR("Target not halted");
1027 return ERROR_TARGET_NOT_HALTED
;
1030 retval
= at91sam7_read_part_info(bank
);
1031 if (retval
!= ERROR_OK
)
1037 static int at91sam7_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1040 struct at91sam7_flash_bank
*at91sam7_info
= bank
->driver_priv
;
1042 if (at91sam7_info
->cidr
== 0)
1044 return ERROR_FLASH_BANK_NOT_PROBED
;
1047 printed
= snprintf(buf
, buf_size
,
1048 "\n at91sam7 driver information: Chip is %s\n",
1049 at91sam7_info
->target_name
);
1052 buf_size
-= printed
;
1054 printed
= snprintf(buf
,
1056 " Cidr: 0x%8.8" PRIx32
" | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32
"\n",
1057 at91sam7_info
->cidr
,
1058 at91sam7_info
->cidr_arch
,
1059 EPROC
[at91sam7_info
->cidr_eproc
],
1060 at91sam7_info
->cidr_version
,
1064 buf_size
-= printed
;
1066 printed
= snprintf(buf
, buf_size
,
1067 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1068 (unsigned)(at91sam7_info
->mck_freq
/ 1000), (unsigned)(at91sam7_info
->ext_freq
/ 1000));
1071 buf_size
-= printed
;
1073 printed
= snprintf(buf
, buf_size
,
1074 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1075 at91sam7_info
->pagesize
, bank
->num_sectors
, at91sam7_info
->num_lockbits_on
,
1076 at91sam7_info
->lockbits
, at91sam7_info
->pages_per_sector
*at91sam7_info
->num_lockbits_on
);
1079 buf_size
-= printed
;
1081 printed
= snprintf(buf
, buf_size
,
1082 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1083 at91sam7_info
->securitybit
, at91sam7_info
->num_nvmbits
,
1084 at91sam7_info
->num_nvmbits_on
, at91sam7_info
->nvmbits
);
1087 buf_size
-= printed
;
1093 * On AT91SAM7S: When the gpnvm bits are set with
1094 * > at91sam7 gpnvm bitnr set
1095 * the changes are not visible in the flash controller status register MC_FSR
1096 * until the processor has been reset.
1097 * On the Olimex board this requires a power cycle.
1098 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1099 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1100 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1102 COMMAND_HANDLER(at91sam7_handle_gpnvm_command
)
1104 struct flash_bank
*bank
;
1108 struct at91sam7_flash_bank
*at91sam7_info
;
1113 command_print(CMD_CTX
, "at91sam7 gpnvm <bit> <set | clear>");
1117 bank
= get_flash_bank_by_num_noprobe(0);
1120 return ERROR_FLASH_BANK_INVALID
;
1122 if (strcmp(bank
->driver
->name
, "at91sam7"))
1124 command_print(CMD_CTX
, "not an at91sam7 flash bank '%s'", CMD_ARGV
[0]);
1125 return ERROR_FLASH_BANK_INVALID
;
1127 if (bank
->target
->state
!= TARGET_HALTED
)
1129 LOG_ERROR("target has to be halted to perform flash operation");
1130 return ERROR_TARGET_NOT_HALTED
;
1133 if (strcmp(CMD_ARGV
[1], "set") == 0)
1137 else if (strcmp(CMD_ARGV
[1], "clear") == 0)
1143 return ERROR_COMMAND_SYNTAX_ERROR
;
1146 at91sam7_info
= bank
->driver_priv
;
1147 if (at91sam7_info
->cidr
== 0)
1149 retval
= at91sam7_read_part_info(bank
);
1150 if (retval
!= ERROR_OK
)
1156 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], bit
);
1157 if ((bit
< 0) || (bit
>= at91sam7_info
->num_nvmbits
))
1159 command_print(CMD_CTX
, "gpnvm bit '#%s' is out of bounds for target %s", CMD_ARGV
[0], at91sam7_info
->target_name
);
1163 /* Configure the flash controller timing */
1164 at91sam7_read_clock_info(bank
);
1165 at91sam7_set_flash_mode(bank
, FMR_TIMING_NVBITS
);
1167 if (at91sam7_flash_command(bank
, flashcmd
, bit
) != ERROR_OK
)
1169 return ERROR_FLASH_OPERATION_FAILED
;
1172 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1173 status
= at91sam7_get_flash_status(bank
->target
, 0);
1174 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32
" \n", flashcmd
, bit
, status
);
1176 /* check protect state */
1177 at91sam7_protect_check(bank
);
1182 static const struct command_registration at91sam7_exec_command_handlers
[] = {
1185 .handler
= at91sam7_handle_gpnvm_command
,
1186 .mode
= COMMAND_EXEC
,
1187 .help
= "set or clear one General Purpose Non-Volatile Memory "
1189 .usage
= "bitnum ('set'|'clear')",
1191 COMMAND_REGISTRATION_DONE
1193 static const struct command_registration at91sam7_command_handlers
[] = {
1196 .mode
= COMMAND_ANY
,
1197 .help
= "at91sam7 flash command group",
1198 .chain
= at91sam7_exec_command_handlers
,
1200 COMMAND_REGISTRATION_DONE
1203 struct flash_driver at91sam7_flash
= {
1205 .commands
= at91sam7_command_handlers
,
1206 .flash_bank_command
= at91sam7_flash_bank_command
,
1207 .erase
= at91sam7_erase
,
1208 .protect
= at91sam7_protect
,
1209 .write
= at91sam7_write
,
1210 .probe
= at91sam7_probe
,
1211 .auto_probe
= at91sam7_probe
,
1212 .erase_check
= at91sam7_erase_check
,
1213 .protect_check
= at91sam7_protect_check
,
1214 .info
= at91sam7_info
,
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