1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2013 by Andrey Yurovsky *
5 * Andrey Yurovsky <yurovsky@gmail.com> *
6 ***************************************************************************/
13 #include "helper/binarybuffer.h"
15 #include <jtag/jtag.h>
16 #include <target/cortex_m.h>
18 #define SAMD_NUM_PROT_BLOCKS 16
19 #define SAMD_PAGE_SIZE_MAX 1024
21 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
22 #define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
23 #define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
24 #define SAMD_DSU 0x41002000 /* Device Service Unit */
25 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
27 #define SAMD_DSU_STATUSA 1 /* DSU status register */
28 #define SAMD_DSU_DID 0x18 /* Device ID register */
29 #define SAMD_DSU_CTRL_EXT 0x100 /* CTRL register, external access */
31 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
32 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
33 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
34 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interrupt Flag Status & Clear */
35 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
36 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
37 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
39 #define SAMD_CMDEX_KEY 0xA5UL
40 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
42 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
43 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
44 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
45 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxiliary Row */
46 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxiliary Page */
47 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
48 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
49 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
50 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
51 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
52 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
53 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
56 #define SAMD_NVM_CTRLB_MANW 0x80
58 /* Known identifiers */
59 #define SAMD_PROCESSOR_M0 0x01
60 #define SAMD_FAMILY_D 0x00
61 #define SAMD_FAMILY_L 0x01
62 #define SAMD_FAMILY_C 0x02
63 #define SAMD_SERIES_20 0x00
64 #define SAMD_SERIES_21 0x01
65 #define SAMD_SERIES_22 0x02
66 #define SAMD_SERIES_10 0x02
67 #define SAMD_SERIES_11 0x03
68 #define SAMD_SERIES_09 0x04
70 /* Device ID macros */
71 #define SAMD_GET_PROCESSOR(id) (id >> 28)
72 #define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
73 #define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
74 #define SAMD_GET_DEVSEL(id) (id & 0xFF)
76 /* Bits to mask out lockbits in user row */
77 #define NVMUSERROW_LOCKBIT_MASK ((uint64_t)0x0000FFFFFFFFFFFF)
86 /* Known SAMD09 parts. DID reset values missing in RM, see
87 * https://github.com/avrxml/asf/blob/master/sam0/utils/cmsis/samd09/include/ */
88 static const struct samd_part samd09_parts
[] = {
89 { 0x0, "SAMD09D14A", 16, 4 },
90 { 0x7, "SAMD09C13A", 8, 4 },
93 /* Known SAMD10 parts */
94 static const struct samd_part samd10_parts
[] = {
95 { 0x0, "SAMD10D14AMU", 16, 4 },
96 { 0x1, "SAMD10D13AMU", 8, 4 },
97 { 0x2, "SAMD10D12AMU", 4, 4 },
98 { 0x3, "SAMD10D14ASU", 16, 4 },
99 { 0x4, "SAMD10D13ASU", 8, 4 },
100 { 0x5, "SAMD10D12ASU", 4, 4 },
101 { 0x6, "SAMD10C14A", 16, 4 },
102 { 0x7, "SAMD10C13A", 8, 4 },
103 { 0x8, "SAMD10C12A", 4, 4 },
106 /* Known SAMD11 parts */
107 static const struct samd_part samd11_parts
[] = {
108 { 0x0, "SAMD11D14AM", 16, 4 },
109 { 0x1, "SAMD11D13AMU", 8, 4 },
110 { 0x2, "SAMD11D12AMU", 4, 4 },
111 { 0x3, "SAMD11D14ASS", 16, 4 },
112 { 0x4, "SAMD11D13ASU", 8, 4 },
113 { 0x5, "SAMD11D12ASU", 4, 4 },
114 { 0x6, "SAMD11C14A", 16, 4 },
115 { 0x7, "SAMD11C13A", 8, 4 },
116 { 0x8, "SAMD11C12A", 4, 4 },
117 { 0x9, "SAMD11D14AU", 16, 4 },
120 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
121 static const struct samd_part samd20_parts
[] = {
122 { 0x0, "SAMD20J18A", 256, 32 },
123 { 0x1, "SAMD20J17A", 128, 16 },
124 { 0x2, "SAMD20J16A", 64, 8 },
125 { 0x3, "SAMD20J15A", 32, 4 },
126 { 0x4, "SAMD20J14A", 16, 2 },
127 { 0x5, "SAMD20G18A", 256, 32 },
128 { 0x6, "SAMD20G17A", 128, 16 },
129 { 0x7, "SAMD20G16A", 64, 8 },
130 { 0x8, "SAMD20G15A", 32, 4 },
131 { 0x9, "SAMD20G14A", 16, 2 },
132 { 0xA, "SAMD20E18A", 256, 32 },
133 { 0xB, "SAMD20E17A", 128, 16 },
134 { 0xC, "SAMD20E16A", 64, 8 },
135 { 0xD, "SAMD20E15A", 32, 4 },
136 { 0xE, "SAMD20E14A", 16, 2 },
139 /* Known SAMD21 parts. */
140 static const struct samd_part samd21_parts
[] = {
141 { 0x0, "SAMD21J18A", 256, 32 },
142 { 0x1, "SAMD21J17A", 128, 16 },
143 { 0x2, "SAMD21J16A", 64, 8 },
144 { 0x3, "SAMD21J15A", 32, 4 },
145 { 0x4, "SAMD21J14A", 16, 2 },
146 { 0x5, "SAMD21G18A", 256, 32 },
147 { 0x6, "SAMD21G17A", 128, 16 },
148 { 0x7, "SAMD21G16A", 64, 8 },
149 { 0x8, "SAMD21G15A", 32, 4 },
150 { 0x9, "SAMD21G14A", 16, 2 },
151 { 0xA, "SAMD21E18A", 256, 32 },
152 { 0xB, "SAMD21E17A", 128, 16 },
153 { 0xC, "SAMD21E16A", 64, 8 },
154 { 0xD, "SAMD21E15A", 32, 4 },
155 { 0xE, "SAMD21E14A", 16, 2 },
157 /* SAMR21 parts have integrated SAMD21 with a radio */
158 { 0x18, "SAMR21G19A", 256, 32 }, /* with 512k of serial flash */
159 { 0x19, "SAMR21G18A", 256, 32 },
160 { 0x1A, "SAMR21G17A", 128, 32 },
161 { 0x1B, "SAMR21G16A", 64, 16 },
162 { 0x1C, "SAMR21E18A", 256, 32 },
163 { 0x1D, "SAMR21E17A", 128, 32 },
164 { 0x1E, "SAMR21E16A", 64, 16 },
166 /* SAMD21 B Variants (Table 3-7 from rev I of datasheet) */
167 { 0x20, "SAMD21J16B", 64, 8 },
168 { 0x21, "SAMD21J15B", 32, 4 },
169 { 0x23, "SAMD21G16B", 64, 8 },
170 { 0x24, "SAMD21G15B", 32, 4 },
171 { 0x26, "SAMD21E16B", 64, 8 },
172 { 0x27, "SAMD21E15B", 32, 4 },
174 /* SAMD21 D and L Variants (from Errata)
175 http://ww1.microchip.com/downloads/en/DeviceDoc/
176 SAM-D21-Family-Silicon-Errata-and-DataSheet-Clarification-DS80000760D.pdf */
177 { 0x55, "SAMD21E16BU", 64, 8 },
178 { 0x56, "SAMD21E15BU", 32, 4 },
179 { 0x57, "SAMD21G16L", 64, 8 },
180 { 0x3E, "SAMD21E16L", 64, 8 },
181 { 0x3F, "SAMD21E15L", 32, 4 },
182 { 0x62, "SAMD21E16CU", 64, 8 },
183 { 0x63, "SAMD21E15CU", 32, 4 },
184 { 0x92, "SAMD21J17D", 128, 16 },
185 { 0x93, "SAMD21G17D", 128, 16 },
186 { 0x94, "SAMD21E17D", 128, 16 },
187 { 0x95, "SAMD21E17DU", 128, 16 },
188 { 0x96, "SAMD21G17L", 128, 16 },
189 { 0x97, "SAMD21E17L", 128, 16 },
191 /* Known SAMDA1 parts.
192 SAMD-A1 series uses the same series identifier like the SAMD21
193 taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
194 { 0x29, "SAMDA1J16A", 64, 8 },
195 { 0x2A, "SAMDA1J15A", 32, 4 },
196 { 0x2B, "SAMDA1J14A", 16, 4 },
197 { 0x2C, "SAMDA1G16A", 64, 8 },
198 { 0x2D, "SAMDA1G15A", 32, 4 },
199 { 0x2E, "SAMDA1G14A", 16, 4 },
200 { 0x2F, "SAMDA1E16A", 64, 8 },
201 { 0x30, "SAMDA1E15A", 32, 4 },
202 { 0x31, "SAMDA1E14A", 16, 4 },
203 { 0x64, "SAMDA1J16B", 64, 8 },
204 { 0x65, "SAMDA1J15B", 32, 4 },
205 { 0x66, "SAMDA1J14B", 16, 4 },
206 { 0x67, "SAMDA1G16B", 64, 8 },
207 { 0x68, "SAMDA1G15B", 32, 4 },
208 { 0x69, "SAMDA1G14B", 16, 4 },
209 { 0x6A, "SAMDA1E16B", 64, 8 },
210 { 0x6B, "SAMDA1E15B", 32, 4 },
211 { 0x6C, "SAMDA1E14B", 16, 4 },
214 /* Known SAML21 parts. */
215 static const struct samd_part saml21_parts
[] = {
216 { 0x00, "SAML21J18A", 256, 32 },
217 { 0x01, "SAML21J17A", 128, 16 },
218 { 0x02, "SAML21J16A", 64, 8 },
219 { 0x05, "SAML21G18A", 256, 32 },
220 { 0x06, "SAML21G17A", 128, 16 },
221 { 0x07, "SAML21G16A", 64, 8 },
222 { 0x0A, "SAML21E18A", 256, 32 },
223 { 0x0B, "SAML21E17A", 128, 16 },
224 { 0x0C, "SAML21E16A", 64, 8 },
225 { 0x0D, "SAML21E15A", 32, 4 },
226 { 0x0F, "SAML21J18B", 256, 32 },
227 { 0x10, "SAML21J17B", 128, 16 },
228 { 0x11, "SAML21J16B", 64, 8 },
229 { 0x14, "SAML21G18B", 256, 32 },
230 { 0x15, "SAML21G17B", 128, 16 },
231 { 0x16, "SAML21G16B", 64, 8 },
232 { 0x19, "SAML21E18B", 256, 32 },
233 { 0x1A, "SAML21E17B", 128, 16 },
234 { 0x1B, "SAML21E16B", 64, 8 },
235 { 0x1C, "SAML21E15B", 32, 4 },
237 /* SAMR30 parts have integrated SAML21 with a radio */
238 { 0x1E, "SAMR30G18A", 256, 32 },
239 { 0x1F, "SAMR30E18A", 256, 32 },
241 /* SAMR34/R35 parts have integrated SAML21 with a lora radio */
242 { 0x28, "SAMR34J18", 256, 32 },
243 { 0x2B, "SAMR35J18", 256, 32 },
246 /* Known SAML22 parts. */
247 static const struct samd_part saml22_parts
[] = {
248 { 0x00, "SAML22N18A", 256, 32 },
249 { 0x01, "SAML22N17A", 128, 16 },
250 { 0x02, "SAML22N16A", 64, 8 },
251 { 0x05, "SAML22J18A", 256, 32 },
252 { 0x06, "SAML22J17A", 128, 16 },
253 { 0x07, "SAML22J16A", 64, 8 },
254 { 0x0A, "SAML22G18A", 256, 32 },
255 { 0x0B, "SAML22G17A", 128, 16 },
256 { 0x0C, "SAML22G16A", 64, 8 },
259 /* Known SAMC20 parts. */
260 static const struct samd_part samc20_parts
[] = {
261 { 0x00, "SAMC20J18A", 256, 32 },
262 { 0x01, "SAMC20J17A", 128, 16 },
263 { 0x02, "SAMC20J16A", 64, 8 },
264 { 0x03, "SAMC20J15A", 32, 4 },
265 { 0x05, "SAMC20G18A", 256, 32 },
266 { 0x06, "SAMC20G17A", 128, 16 },
267 { 0x07, "SAMC20G16A", 64, 8 },
268 { 0x08, "SAMC20G15A", 32, 4 },
269 { 0x0A, "SAMC20E18A", 256, 32 },
270 { 0x0B, "SAMC20E17A", 128, 16 },
271 { 0x0C, "SAMC20E16A", 64, 8 },
272 { 0x0D, "SAMC20E15A", 32, 4 },
273 { 0x20, "SAMC20N18A", 256, 32 },
274 { 0x21, "SAMC20N17A", 128, 16 },
277 /* Known SAMC21 parts. */
278 static const struct samd_part samc21_parts
[] = {
279 { 0x00, "SAMC21J18A", 256, 32 },
280 { 0x01, "SAMC21J17A", 128, 16 },
281 { 0x02, "SAMC21J16A", 64, 8 },
282 { 0x03, "SAMC21J15A", 32, 4 },
283 { 0x05, "SAMC21G18A", 256, 32 },
284 { 0x06, "SAMC21G17A", 128, 16 },
285 { 0x07, "SAMC21G16A", 64, 8 },
286 { 0x08, "SAMC21G15A", 32, 4 },
287 { 0x0A, "SAMC21E18A", 256, 32 },
288 { 0x0B, "SAMC21E17A", 128, 16 },
289 { 0x0C, "SAMC21E16A", 64, 8 },
290 { 0x0D, "SAMC21E15A", 32, 4 },
291 { 0x20, "SAMC21N18A", 256, 32 },
292 { 0x21, "SAMC21N17A", 128, 16 },
295 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
296 * processor ID, family ID, and series ID are used to determine which exact
297 * family this is and then we can use the corresponding table. */
302 const struct samd_part
*parts
;
304 uint64_t nvm_userrow_res_mask
; /* protect bits which are reserved, 0 -> protect */
307 /* Known SAMD families */
308 static const struct samd_family samd_families
[] = {
309 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_20
,
310 samd20_parts
, ARRAY_SIZE(samd20_parts
),
311 (uint64_t)0xFFFF01FFFE01FF77 },
312 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_21
,
313 samd21_parts
, ARRAY_SIZE(samd21_parts
),
314 (uint64_t)0xFFFF01FFFE01FF77 },
315 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_09
,
316 samd09_parts
, ARRAY_SIZE(samd09_parts
),
317 (uint64_t)0xFFFF01FFFE01FF77 },
318 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_10
,
319 samd10_parts
, ARRAY_SIZE(samd10_parts
),
320 (uint64_t)0xFFFF01FFFE01FF77 },
321 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_D
, SAMD_SERIES_11
,
322 samd11_parts
, ARRAY_SIZE(samd11_parts
),
323 (uint64_t)0xFFFF01FFFE01FF77 },
324 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_21
,
325 saml21_parts
, ARRAY_SIZE(saml21_parts
),
326 (uint64_t)0xFFFF03FFFC01FF77 },
327 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_L
, SAMD_SERIES_22
,
328 saml22_parts
, ARRAY_SIZE(saml22_parts
),
329 (uint64_t)0xFFFF03FFFC01FF77 },
330 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_20
,
331 samc20_parts
, ARRAY_SIZE(samc20_parts
),
332 (uint64_t)0xFFFF03FFFC01FF77 },
333 { SAMD_PROCESSOR_M0
, SAMD_FAMILY_C
, SAMD_SERIES_21
,
334 samc21_parts
, ARRAY_SIZE(samc21_parts
),
335 (uint64_t)0xFFFF03FFFC01FF77 },
345 struct target
*target
;
350 * Gives the family structure to specific device id.
351 * @param id The id of the device.
352 * @return On failure NULL, otherwise a pointer to the structure.
354 static const struct samd_family
*samd_find_family(uint32_t id
)
356 uint8_t processor
= SAMD_GET_PROCESSOR(id
);
357 uint8_t family
= SAMD_GET_FAMILY(id
);
358 uint8_t series
= SAMD_GET_SERIES(id
);
360 for (unsigned i
= 0; i
< ARRAY_SIZE(samd_families
); i
++) {
361 if (samd_families
[i
].processor
== processor
&&
362 samd_families
[i
].series
== series
&&
363 samd_families
[i
].family
== family
)
364 return &samd_families
[i
];
371 * Gives the part structure to specific device id.
372 * @param id The id of the device.
373 * @return On failure NULL, otherwise a pointer to the structure.
375 static const struct samd_part
*samd_find_part(uint32_t id
)
377 uint8_t devsel
= SAMD_GET_DEVSEL(id
);
378 const struct samd_family
*family
= samd_find_family(id
);
382 for (unsigned i
= 0; i
< family
->num_parts
; i
++) {
383 if (family
->parts
[i
].id
== devsel
)
384 return &family
->parts
[i
];
390 static int samd_protect_check(struct flash_bank
*bank
)
395 res
= target_read_u16(bank
->target
,
396 SAMD_NVMCTRL
+ SAMD_NVMCTRL_LOCK
, &lock
);
400 /* Lock bits are active-low */
401 for (unsigned int prot_block
= 0; prot_block
< bank
->num_prot_blocks
; prot_block
++)
402 bank
->prot_blocks
[prot_block
].is_protected
= !(lock
& (1u<<prot_block
));
407 static int samd_get_flash_page_info(struct target
*target
,
408 uint32_t *sizep
, int *nump
)
413 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_PARAM
, ¶m
);
414 if (res
== ERROR_OK
) {
415 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
416 * so 0 is 8KB and 7 is 1024KB. */
418 *sizep
= (8 << ((param
>> 16) & 0x7));
419 /* The NVMP field (bits 15:0) indicates the total number of pages */
421 *nump
= param
& 0xFFFF;
423 LOG_ERROR("Couldn't read NVM Parameters register");
429 static int samd_probe(struct flash_bank
*bank
)
433 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
434 const struct samd_part
*part
;
439 res
= target_read_u32(bank
->target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
440 if (res
!= ERROR_OK
) {
441 LOG_ERROR("Couldn't read Device ID register");
445 part
= samd_find_part(id
);
447 LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32
, id
);
451 bank
->size
= part
->flash_kb
* 1024;
453 res
= samd_get_flash_page_info(bank
->target
, &chip
->page_size
,
455 if (res
!= ERROR_OK
) {
456 LOG_ERROR("Couldn't determine Flash page size");
460 /* Sanity check: the total flash size in the DSU should match the page size
461 * multiplied by the number of pages. */
462 if (bank
->size
!= chip
->num_pages
* chip
->page_size
) {
463 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
464 "Identified %" PRIu32
"KB Flash but NVMCTRL reports %u %" PRIu32
"B pages",
465 part
->flash_kb
, chip
->num_pages
, chip
->page_size
);
468 /* Erase granularity = 1 row = 4 pages */
469 chip
->sector_size
= chip
->page_size
* 4;
471 /* Allocate the sector table */
472 bank
->num_sectors
= chip
->num_pages
/ 4;
473 bank
->sectors
= alloc_block_array(0, chip
->sector_size
, bank
->num_sectors
);
477 /* 16 protection blocks per device */
478 chip
->prot_block_size
= bank
->size
/ SAMD_NUM_PROT_BLOCKS
;
480 /* Allocate the table of protection blocks */
481 bank
->num_prot_blocks
= SAMD_NUM_PROT_BLOCKS
;
482 bank
->prot_blocks
= alloc_block_array(0, chip
->prot_block_size
, bank
->num_prot_blocks
);
483 if (!bank
->prot_blocks
)
486 samd_protect_check(bank
);
491 LOG_INFO("SAMD MCU: %s (%" PRIu32
"KB Flash, %" PRIu32
"KB RAM)", part
->name
,
492 part
->flash_kb
, part
->ram_kb
);
497 static int samd_check_error(struct target
*target
)
502 ret
= target_read_u16(target
,
503 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, &status
);
504 if (ret
!= ERROR_OK
) {
505 LOG_ERROR("Can't read NVM status");
509 if ((status
& 0x001C) == 0)
512 if (status
& (1 << 4)) { /* NVME */
513 LOG_ERROR("SAMD: NVM Error");
514 ret
= ERROR_FLASH_OPERATION_FAILED
;
517 if (status
& (1 << 3)) { /* LOCKE */
518 LOG_ERROR("SAMD: NVM lock error");
519 ret
= ERROR_FLASH_PROTECTED
;
522 if (status
& (1 << 2)) { /* PROGE */
523 LOG_ERROR("SAMD: NVM programming error");
524 ret
= ERROR_FLASH_OPER_UNSUPPORTED
;
527 /* Clear the error conditions by writing a one to them */
528 ret2
= target_write_u16(target
,
529 SAMD_NVMCTRL
+ SAMD_NVMCTRL_STATUS
, status
);
530 if (ret2
!= ERROR_OK
)
531 LOG_ERROR("Can't clear NVM error conditions");
536 static int samd_issue_nvmctrl_command(struct target
*target
, uint16_t cmd
)
540 if (target
->state
!= TARGET_HALTED
) {
541 LOG_ERROR("Target not halted");
542 return ERROR_TARGET_NOT_HALTED
;
545 /* Issue the NVM command */
546 /* 32-bit write is used to ensure atomic operation on ST-Link */
547 res
= target_write_u32(target
,
548 SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLA
, SAMD_NVM_CMD(cmd
));
552 /* Check to see if the NVM command resulted in an error condition. */
553 return samd_check_error(target
);
557 * Erases a flash-row at the given address.
558 * @param target Pointer to the target structure.
559 * @param address The address of the row.
560 * @return On success ERROR_OK, on failure an errorcode.
562 static int samd_erase_row(struct target
*target
, uint32_t address
)
566 /* Set an address contained in the row to be erased */
567 res
= target_write_u32(target
,
568 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
, address
>> 1);
570 /* Issue the Erase Row command to erase that row. */
572 res
= samd_issue_nvmctrl_command(target
,
573 address
== SAMD_USER_ROW
? SAMD_NVM_CMD_EAR
: SAMD_NVM_CMD_ER
);
575 if (res
!= ERROR_OK
) {
576 LOG_ERROR("Failed to erase row containing %08" PRIx32
, address
);
584 * Returns the bitmask of reserved bits in register.
585 * @param target Pointer to the target structure.
586 * @param mask Bitmask, 0 -> value stays untouched.
587 * @return On success ERROR_OK, on failure an errorcode.
589 static int samd_get_reservedmask(struct target
*target
, uint64_t *mask
)
592 /* Get the devicetype */
594 res
= target_read_u32(target
, SAMD_DSU
+ SAMD_DSU_DID
, &id
);
595 if (res
!= ERROR_OK
) {
596 LOG_ERROR("Couldn't read Device ID register");
599 const struct samd_family
*family
;
600 family
= samd_find_family(id
);
602 LOG_ERROR("Couldn't determine device family");
605 *mask
= family
->nvm_userrow_res_mask
;
609 static int read_userrow(struct target
*target
, uint64_t *userrow
)
614 res
= target_read_memory(target
, SAMD_USER_ROW
, 4, 2, buffer
);
618 *userrow
= target_buffer_get_u64(target
, buffer
);
623 * Modify the contents of the User Row in Flash. The User Row itself
624 * has a size of one page and contains a combination of "fuses" and
625 * calibration data. Bits which have a value of zero in the mask will
626 * not be changed. Up to now devices only use the first 64 bits.
627 * @param target Pointer to the target structure.
628 * @param value_input The value to write.
629 * @param value_mask Bitmask, 0 -> value stays untouched.
630 * @return On success ERROR_OK, on failure an errorcode.
632 static int samd_modify_user_row_masked(struct target
*target
,
633 uint64_t value_input
, uint64_t value_mask
)
637 bool manual_wp
= true;
639 /* Retrieve the MCU's page size, in bytes. This is also the size of the
640 * entire User Row. */
642 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
643 if (res
!= ERROR_OK
) {
644 LOG_ERROR("Couldn't determine Flash page size");
648 /* Make sure the size is sane. */
649 assert(page_size
<= SAMD_PAGE_SIZE_MAX
&&
650 page_size
>= sizeof(value_input
));
652 uint8_t buf
[SAMD_PAGE_SIZE_MAX
];
653 /* Read the user row (comprising one page) by words. */
654 res
= target_read_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
658 uint64_t value_device
;
659 res
= read_userrow(target
, &value_device
);
662 uint64_t value_new
= (value_input
& value_mask
) | (value_device
& ~value_mask
);
664 /* We will need to erase before writing if the new value needs a '1' in any
665 * position for which the current value had a '0'. Otherwise we can avoid
667 if ((~value_device
) & value_new
) {
668 res
= samd_erase_row(target
, SAMD_USER_ROW
);
669 if (res
!= ERROR_OK
) {
670 LOG_ERROR("Couldn't erase user row");
676 target_buffer_set_u64(target
, buf
, value_new
);
678 /* Write the page buffer back out to the target. */
679 res
= target_write_memory(target
, SAMD_USER_ROW
, 4, page_size
/ 4, buf
);
683 /* Check if we need to do manual page write commands */
684 res
= target_read_u32(target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
686 manual_wp
= (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
) != 0;
688 LOG_ERROR("Read of NVM register CTRKB failed.");
692 /* Trigger flash write */
693 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_WAP
);
695 res
= samd_check_error(target
);
702 * Modifies the user row register to the given value.
703 * @param target Pointer to the target structure.
704 * @param value The value to write.
705 * @param startb The bit-offset by which the given value is shifted.
706 * @param endb The bit-offset of the last bit in value to write.
707 * @return On success ERROR_OK, on failure an errorcode.
709 static int samd_modify_user_row(struct target
*target
, uint64_t value
,
710 uint8_t startb
, uint8_t endb
)
714 for (i
= startb
; i
<= endb
; i
++)
715 mask
|= ((uint64_t)1) << i
;
717 return samd_modify_user_row_masked(target
, value
<< startb
, mask
);
720 static int samd_protect(struct flash_bank
*bank
, int set
,
721 unsigned int first
, unsigned int last
)
725 /* We can issue lock/unlock region commands with the target running but
726 * the settings won't persist unless we're able to modify the LOCK regions
727 * and that requires the target to be halted. */
728 if (bank
->target
->state
!= TARGET_HALTED
) {
729 LOG_ERROR("Target not halted");
730 return ERROR_TARGET_NOT_HALTED
;
733 for (unsigned int prot_block
= first
; prot_block
<= last
; prot_block
++) {
734 if (set
!= bank
->prot_blocks
[prot_block
].is_protected
) {
735 /* Load an address that is within this protection block (we use offset 0) */
736 res
= target_write_u32(bank
->target
,
737 SAMD_NVMCTRL
+ SAMD_NVMCTRL_ADDR
,
738 bank
->prot_blocks
[prot_block
].offset
>> 1);
742 /* Tell the controller to lock that block */
743 res
= samd_issue_nvmctrl_command(bank
->target
,
744 set
? SAMD_NVM_CMD_LR
: SAMD_NVM_CMD_UR
);
750 /* We've now applied our changes, however they will be undone by the next
751 * reset unless we also apply them to the LOCK bits in the User Page. The
752 * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
753 * corresponding to Sector 15. A '1' means unlocked and a '0' means
754 * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
756 res
= samd_modify_user_row(bank
->target
,
757 set
? (uint64_t)0 : (uint64_t)UINT64_MAX
,
758 48 + first
, 48 + last
);
760 LOG_WARNING("SAMD: protect settings were not made persistent!");
765 samd_protect_check(bank
);
770 static int samd_erase(struct flash_bank
*bank
, unsigned int first
,
774 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
776 if (bank
->target
->state
!= TARGET_HALTED
) {
777 LOG_ERROR("Target not halted");
779 return ERROR_TARGET_NOT_HALTED
;
783 if (samd_probe(bank
) != ERROR_OK
)
784 return ERROR_FLASH_BANK_NOT_PROBED
;
787 /* For each sector to be erased */
788 for (unsigned int s
= first
; s
<= last
; s
++) {
789 res
= samd_erase_row(bank
->target
, bank
->sectors
[s
].offset
);
790 if (res
!= ERROR_OK
) {
791 LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32
, s
, bank
->sectors
[s
].offset
);
800 static int samd_write(struct flash_bank
*bank
, const uint8_t *buffer
,
801 uint32_t offset
, uint32_t count
)
809 struct samd_info
*chip
= (struct samd_info
*)bank
->driver_priv
;
813 if (bank
->target
->state
!= TARGET_HALTED
) {
814 LOG_ERROR("Target not halted");
815 return ERROR_TARGET_NOT_HALTED
;
819 if (samd_probe(bank
) != ERROR_OK
)
820 return ERROR_FLASH_BANK_NOT_PROBED
;
823 /* Check if we need to do manual page write commands */
824 res
= target_read_u32(bank
->target
, SAMD_NVMCTRL
+ SAMD_NVMCTRL_CTRLB
, &nvm_ctrlb
);
829 if (nvm_ctrlb
& SAMD_NVM_CTRLB_MANW
)
834 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_PBC
);
835 if (res
!= ERROR_OK
) {
836 LOG_ERROR("%s: %d", __func__
, __LINE__
);
841 nb
= chip
->page_size
- offset
% chip
->page_size
;
845 address
= bank
->base
+ offset
;
846 pg_offset
= offset
% chip
->page_size
;
848 if (offset
% 4 || (offset
+ nb
) % 4) {
849 /* Either start or end of write is not word aligned */
851 pb
= malloc(chip
->page_size
);
856 /* Set temporary page buffer to 0xff and overwrite the relevant part */
857 memset(pb
, 0xff, chip
->page_size
);
858 memcpy(pb
+ pg_offset
, buffer
, nb
);
860 /* Align start address to a word boundary */
861 address
-= offset
% 4;
862 pg_offset
-= offset
% 4;
863 assert(pg_offset
% 4 == 0);
865 /* Extend length to whole words */
866 nw
= (nb
+ offset
% 4 + 3) / 4;
867 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
869 /* Now we have original data extended by 0xff bytes
870 * to the nearest word boundary on both start and end */
871 res
= target_write_memory(bank
->target
, address
, 4, nw
, pb
+ pg_offset
);
875 assert(pg_offset
+ 4 * nw
<= chip
->page_size
);
877 /* Word aligned data, use direct write from buffer */
878 res
= target_write_memory(bank
->target
, address
, 4, nw
, buffer
);
880 if (res
!= ERROR_OK
) {
881 LOG_ERROR("%s: %d", __func__
, __LINE__
);
885 /* Devices with errata 13134 have automatic page write enabled by default
886 * For other devices issue a write page CMD to the NVM
887 * If the page has not been written up to the last word
888 * then issue CMD_WP always */
889 if (manual_wp
|| pg_offset
+ 4 * nw
< chip
->page_size
) {
890 res
= samd_issue_nvmctrl_command(bank
->target
, SAMD_NVM_CMD_WP
);
892 /* Access through AHB is stalled while flash is being programmed */
895 res
= samd_check_error(bank
->target
);
898 if (res
!= ERROR_OK
) {
899 LOG_ERROR("%s: write failed at address 0x%08" PRIx32
, __func__
, address
);
903 /* We're done with the page contents */
914 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command
)
916 if (bank
->base
!= SAMD_FLASH
) {
917 LOG_ERROR("Address " TARGET_ADDR_FMT
918 " invalid bank address (try 0x%08" PRIx32
919 "[at91samd series] )",
920 bank
->base
, SAMD_FLASH
);
924 struct samd_info
*chip
;
925 chip
= calloc(1, sizeof(*chip
));
927 LOG_ERROR("No memory for flash bank chip info");
931 chip
->target
= bank
->target
;
932 chip
->probed
= false;
934 bank
->driver_priv
= chip
;
939 COMMAND_HANDLER(samd_handle_chip_erase_command
)
941 struct target
*target
= get_current_target(CMD_CTX
);
942 int res
= ERROR_FAIL
;
945 /* Enable access to the DSU by disabling the write protect bit */
946 target_write_u32(target
, SAMD_PAC1
, (1<<1));
947 /* intentionally without error checking - not accessible on secured chip */
949 /* Tell the DSU to perform a full chip erase. It takes about 240ms to
950 * perform the erase. */
951 res
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_CTRL_EXT
, (1<<4));
953 command_print(CMD
, "chip erase started");
955 command_print(CMD
, "write to DSU CTRL failed");
961 COMMAND_HANDLER(samd_handle_set_security_command
)
964 struct target
*target
= get_current_target(CMD_CTX
);
966 if (CMD_ARGC
< 1 || (CMD_ARGC
>= 1 && (strcmp(CMD_ARGV
[0], "enable")))) {
967 command_print(CMD
, "supply the \"enable\" argument to proceed.");
968 return ERROR_COMMAND_SYNTAX_ERROR
;
972 if (target
->state
!= TARGET_HALTED
) {
973 LOG_ERROR("Target not halted");
974 return ERROR_TARGET_NOT_HALTED
;
977 res
= samd_issue_nvmctrl_command(target
, SAMD_NVM_CMD_SSB
);
979 /* Check (and clear) error conditions */
981 command_print(CMD
, "chip secured on next power-cycle");
983 command_print(CMD
, "failed to secure chip");
989 COMMAND_HANDLER(samd_handle_eeprom_command
)
992 struct target
*target
= get_current_target(CMD_CTX
);
995 if (target
->state
!= TARGET_HALTED
) {
996 LOG_ERROR("Target not halted");
997 return ERROR_TARGET_NOT_HALTED
;
1000 if (CMD_ARGC
>= 1) {
1001 int val
= atoi(CMD_ARGV
[0]);
1007 /* Try to match size in bytes with corresponding size code */
1008 for (code
= 0; code
<= 6; code
++) {
1009 if (val
== (2 << (13 - code
)))
1014 command_print(CMD
, "Invalid EEPROM size. Please see "
1015 "datasheet for a list valid sizes.");
1016 return ERROR_COMMAND_SYNTAX_ERROR
;
1020 res
= samd_modify_user_row(target
, code
, 4, 6);
1023 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
1024 if (res
== ERROR_OK
) {
1025 uint32_t size
= ((val
>> 4) & 0x7); /* grab size code */
1028 command_print(CMD
, "EEPROM is disabled");
1030 /* Otherwise, 6 is 256B, 0 is 16KB */
1031 command_print(CMD
, "EEPROM size is %u bytes",
1032 (2 << (13 - size
)));
1041 COMMAND_HANDLER(samd_handle_nvmuserrow_command
)
1044 struct target
*target
= get_current_target(CMD_CTX
);
1048 command_print(CMD
, "Too much Arguments given.");
1049 return ERROR_COMMAND_SYNTAX_ERROR
;
1053 if (target
->state
!= TARGET_HALTED
) {
1054 LOG_ERROR("Target not halted.");
1055 return ERROR_TARGET_NOT_HALTED
;
1059 res
= samd_get_reservedmask(target
, &mask
);
1060 if (res
!= ERROR_OK
) {
1061 LOG_ERROR("Couldn't determine the mask for reserved bits.");
1064 mask
&= NVMUSERROW_LOCKBIT_MASK
;
1067 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[0], value
);
1069 if (CMD_ARGC
== 2) {
1071 COMMAND_PARSE_NUMBER(u64
, CMD_ARGV
[1], mask_temp
);
1075 res
= samd_modify_user_row_masked(target
, value
, mask
);
1076 if (res
!= ERROR_OK
)
1082 res
= read_userrow(target
, &value
);
1083 if (res
== ERROR_OK
)
1084 command_print(CMD
, "NVMUSERROW: 0x%016"PRIX64
, value
);
1086 LOG_ERROR("NVMUSERROW could not be read.");
1091 COMMAND_HANDLER(samd_handle_bootloader_command
)
1094 struct target
*target
= get_current_target(CMD_CTX
);
1097 if (target
->state
!= TARGET_HALTED
) {
1098 LOG_ERROR("Target not halted");
1099 return ERROR_TARGET_NOT_HALTED
;
1102 /* Retrieve the MCU's page size, in bytes. */
1104 res
= samd_get_flash_page_info(target
, &page_size
, NULL
);
1105 if (res
!= ERROR_OK
) {
1106 LOG_ERROR("Couldn't determine Flash page size");
1110 if (CMD_ARGC
>= 1) {
1111 int val
= atoi(CMD_ARGV
[0]);
1117 /* Try to match size in bytes with corresponding size code */
1118 for (code
= 0; code
<= 6; code
++) {
1119 if ((unsigned int)val
== (2UL << (8UL - code
)) * page_size
)
1124 command_print(CMD
, "Invalid bootloader size. Please "
1125 "see datasheet for a list valid sizes.");
1126 return ERROR_COMMAND_SYNTAX_ERROR
;
1131 res
= samd_modify_user_row(target
, code
, 0, 2);
1134 res
= target_read_u16(target
, SAMD_USER_ROW
, &val
);
1135 if (res
== ERROR_OK
) {
1136 uint32_t size
= (val
& 0x7); /* grab size code */
1142 nb
= (2 << (8 - size
)) * page_size
;
1144 /* There are 4 pages per row */
1145 command_print(CMD
, "Bootloader size is %" PRIu32
" bytes (%" PRIu32
" rows)",
1146 nb
, (uint32_t)(nb
/ (page_size
* 4)));
1156 COMMAND_HANDLER(samd_handle_reset_deassert
)
1158 struct target
*target
= get_current_target(CMD_CTX
);
1159 int retval
= ERROR_OK
;
1160 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1162 /* If the target has been unresponsive before, try to re-establish
1163 * communication now - CPU is held in reset by DSU, DAP is working */
1164 if (!target_was_examined(target
))
1165 target_examine_one(target
);
1166 target_poll(target
);
1168 /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
1169 * so we just release reset held by DSU
1171 * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
1173 * After vectreset DSU release is not needed however makes no harm
1175 if (target
->reset_halt
&& (jtag_reset_config
& RESET_HAS_SRST
)) {
1176 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| C_HALT
| C_DEBUGEN
);
1177 if (retval
== ERROR_OK
)
1178 retval
= target_write_u32(target
, DCB_DEMCR
,
1179 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1180 /* do not return on error here, releasing DSU reset is more important */
1183 /* clear CPU Reset Phase Extension bit */
1184 int retval2
= target_write_u8(target
, SAMD_DSU
+ SAMD_DSU_STATUSA
, (1<<1));
1185 if (retval2
!= ERROR_OK
)
1191 static const struct command_registration at91samd_exec_command_handlers
[] = {
1193 .name
= "dsu_reset_deassert",
1194 .handler
= samd_handle_reset_deassert
,
1195 .mode
= COMMAND_EXEC
,
1196 .help
= "Deassert internal reset held by DSU.",
1200 .name
= "chip-erase",
1201 .handler
= samd_handle_chip_erase_command
,
1202 .mode
= COMMAND_EXEC
,
1203 .help
= "Erase the entire Flash by using the Chip-"
1204 "Erase feature in the Device Service Unit (DSU).",
1208 .name
= "set-security",
1209 .handler
= samd_handle_set_security_command
,
1210 .mode
= COMMAND_EXEC
,
1211 .help
= "Secure the chip's Flash by setting the Security Bit. "
1212 "This makes it impossible to read the Flash contents. "
1213 "The only way to undo this is to issue the chip-erase "
1215 .usage
= "'enable'",
1219 .usage
= "[size_in_bytes]",
1220 .handler
= samd_handle_eeprom_command
,
1221 .mode
= COMMAND_EXEC
,
1222 .help
= "Show or set the EEPROM size setting, stored in the User Row. "
1223 "Please see Table 20-3 of the SAMD20 datasheet for allowed values. "
1224 "Changes are stored immediately but take affect after the MCU is "
1228 .name
= "bootloader",
1229 .usage
= "[size_in_bytes]",
1230 .handler
= samd_handle_bootloader_command
,
1231 .mode
= COMMAND_EXEC
,
1232 .help
= "Show or set the bootloader size, stored in the User Row. "
1233 "Please see Table 20-2 of the SAMD20 datasheet for allowed values. "
1234 "Changes are stored immediately but take affect after the MCU is "
1238 .name
= "nvmuserrow",
1239 .usage
= "[value] [mask]",
1240 .handler
= samd_handle_nvmuserrow_command
,
1241 .mode
= COMMAND_EXEC
,
1242 .help
= "Show or set the nvmuserrow register. It is 64 bit wide "
1243 "and located at address 0x804000. Use the optional mask argument "
1244 "to prevent changes at positions where the bitvalue is zero. "
1245 "For security reasons the lock- and reserved-bits are masked out "
1246 "in background and therefore cannot be changed.",
1248 COMMAND_REGISTRATION_DONE
1251 static const struct command_registration at91samd_command_handlers
[] = {
1254 .mode
= COMMAND_ANY
,
1255 .help
= "at91samd flash command group",
1257 .chain
= at91samd_exec_command_handlers
,
1259 COMMAND_REGISTRATION_DONE
1262 const struct flash_driver at91samd_flash
= {
1264 .commands
= at91samd_command_handlers
,
1265 .flash_bank_command
= samd_flash_bank_command
,
1266 .erase
= samd_erase
,
1267 .protect
= samd_protect
,
1268 .write
= samd_write
,
1269 .read
= default_flash_read
,
1270 .probe
= samd_probe
,
1271 .auto_probe
= samd_probe
,
1272 .erase_check
= default_flash_blank_check
,
1273 .protect_check
= samd_protect_check
,
1274 .free_driver_priv
= default_flash_free_driver_priv
,
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