1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32x register locations */
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
62 /* option byte location */
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
73 /* FLASH_CR register bits */
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
84 /* FLASH_SR register bits */
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
91 /* STM32_FLASH_OBR bit definitions (reading) */
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
100 /* register unlock keys */
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
105 struct stm32x_options
{
107 uint16_t user_options
;
108 uint16_t protection
[4];
111 struct stm32x_flash_bank
{
112 struct stm32x_options option_bytes
;
113 struct working_area
*write_algorithm
;
118 /* used to access dual flash bank stm32xl */
119 uint32_t register_base
;
122 static int stm32x_mass_erase(struct flash_bank
*bank
);
123 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
125 /* flash bank stm32x <base> <size> 0 0 <target#>
127 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
129 struct stm32x_flash_bank
*stm32x_info
;
132 return ERROR_COMMAND_SYNTAX_ERROR
;
134 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
136 bank
->driver_priv
= stm32x_info
;
137 stm32x_info
->write_algorithm
= NULL
;
138 stm32x_info
->probed
= 0;
139 stm32x_info
->has_dual_banks
= false;
140 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
145 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
147 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
148 return reg
+ stm32x_info
->register_base
;
151 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
153 struct target
*target
= bank
->target
;
154 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
157 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
159 struct target
*target
= bank
->target
;
161 int retval
= ERROR_OK
;
163 /* wait for busy to clear */
165 retval
= stm32x_get_flash_status(bank
, &status
);
166 if (retval
!= ERROR_OK
)
168 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
169 if ((status
& FLASH_BSY
) == 0)
171 if (timeout
-- <= 0) {
172 LOG_ERROR("timed out waiting for flash");
178 if (status
& FLASH_WRPRTERR
) {
179 LOG_ERROR("stm32x device protected");
183 if (status
& FLASH_PGERR
) {
184 LOG_ERROR("stm32x device programming failed");
188 /* Clear but report errors */
189 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
190 /* If this operation fails, we ignore it and report the original
193 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
194 FLASH_WRPRTERR
| FLASH_PGERR
);
199 int stm32x_check_operation_supported(struct flash_bank
*bank
)
201 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
203 /* if we have a dual flash bank device then
204 * we need to perform option byte stuff on bank0 only */
205 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
206 LOG_ERROR("Option Byte Operation's must use bank0");
207 return ERROR_FLASH_OPERATION_FAILED
;
213 static int stm32x_read_options(struct flash_bank
*bank
)
216 struct stm32x_flash_bank
*stm32x_info
= NULL
;
217 struct target
*target
= bank
->target
;
219 stm32x_info
= bank
->driver_priv
;
221 /* read current option bytes */
222 int retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optiondata
);
223 if (retval
!= ERROR_OK
)
226 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
227 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
229 if (optiondata
& (1 << OPT_READOUT
))
230 LOG_INFO("Device Security Bit Set");
232 /* each bit refers to a 4bank protection */
233 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &optiondata
);
234 if (retval
!= ERROR_OK
)
237 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
238 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
239 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
240 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
245 static int stm32x_erase_options(struct flash_bank
*bank
)
247 struct stm32x_flash_bank
*stm32x_info
= NULL
;
248 struct target
*target
= bank
->target
;
250 stm32x_info
= bank
->driver_priv
;
252 /* read current options */
253 stm32x_read_options(bank
);
255 /* unlock flash registers */
256 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
257 if (retval
!= ERROR_OK
)
260 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
261 if (retval
!= ERROR_OK
)
264 /* unlock option flash registers */
265 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
266 if (retval
!= ERROR_OK
)
268 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
269 if (retval
!= ERROR_OK
)
272 /* erase option bytes */
273 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
274 if (retval
!= ERROR_OK
)
276 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
277 if (retval
!= ERROR_OK
)
280 retval
= stm32x_wait_status_busy(bank
, 10);
281 if (retval
!= ERROR_OK
)
284 /* clear readout protection and complementary option bytes
285 * this will also force a device unlock if set */
286 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
291 static int stm32x_write_options(struct flash_bank
*bank
)
293 struct stm32x_flash_bank
*stm32x_info
= NULL
;
294 struct target
*target
= bank
->target
;
296 stm32x_info
= bank
->driver_priv
;
298 /* unlock flash registers */
299 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
300 if (retval
!= ERROR_OK
)
302 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
303 if (retval
!= ERROR_OK
)
306 /* unlock option flash registers */
307 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
308 if (retval
!= ERROR_OK
)
310 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
311 if (retval
!= ERROR_OK
)
314 /* program option bytes */
315 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
316 if (retval
!= ERROR_OK
)
319 /* write user option byte */
320 retval
= target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
321 if (retval
!= ERROR_OK
)
324 retval
= stm32x_wait_status_busy(bank
, 10);
325 if (retval
!= ERROR_OK
)
328 /* write protection byte 1 */
329 retval
= target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
330 if (retval
!= ERROR_OK
)
333 retval
= stm32x_wait_status_busy(bank
, 10);
334 if (retval
!= ERROR_OK
)
337 /* write protection byte 2 */
338 retval
= target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
339 if (retval
!= ERROR_OK
)
342 retval
= stm32x_wait_status_busy(bank
, 10);
343 if (retval
!= ERROR_OK
)
346 /* write protection byte 3 */
347 retval
= target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
348 if (retval
!= ERROR_OK
)
351 retval
= stm32x_wait_status_busy(bank
, 10);
352 if (retval
!= ERROR_OK
)
355 /* write protection byte 4 */
356 retval
= target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
357 if (retval
!= ERROR_OK
)
360 retval
= stm32x_wait_status_busy(bank
, 10);
361 if (retval
!= ERROR_OK
)
364 /* write readout protection bit */
365 retval
= target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
366 if (retval
!= ERROR_OK
)
369 retval
= stm32x_wait_status_busy(bank
, 10);
370 if (retval
!= ERROR_OK
)
373 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
374 if (retval
!= ERROR_OK
)
380 static int stm32x_protect_check(struct flash_bank
*bank
)
382 struct target
*target
= bank
->target
;
383 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
390 if (target
->state
!= TARGET_HALTED
) {
391 LOG_ERROR("Target not halted");
392 return ERROR_TARGET_NOT_HALTED
;
395 int retval
= stm32x_check_operation_supported(bank
);
396 if (ERROR_OK
!= retval
)
399 /* medium density - each bit refers to a 4bank protection
400 * high density - each bit refers to a 2bank protection */
401 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
402 if (retval
!= ERROR_OK
)
405 /* medium density - each protection bit is for 4 * 1K pages
406 * high density - each protection bit is for 2 * 2K pages */
407 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
409 if (stm32x_info
->ppage_size
== 2) {
410 /* high density flash/connectivity line protection */
414 if (protection
& (1 << 31))
417 /* bit 31 controls sector 62 - 255 protection for high density
418 * bit 31 controls sector 62 - 127 protection for connectivity line */
419 for (s
= 62; s
< bank
->num_sectors
; s
++)
420 bank
->sectors
[s
].is_protected
= set
;
422 if (bank
->num_sectors
> 61)
425 for (i
= 0; i
< num_bits
; i
++) {
428 if (protection
& (1 << i
))
431 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
432 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
435 /* low/medium density flash protection */
436 for (i
= 0; i
< num_bits
; i
++) {
439 if (protection
& (1 << i
))
442 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
443 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
450 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
452 struct target
*target
= bank
->target
;
455 if (bank
->target
->state
!= TARGET_HALTED
) {
456 LOG_ERROR("Target not halted");
457 return ERROR_TARGET_NOT_HALTED
;
460 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
461 return stm32x_mass_erase(bank
);
463 /* unlock flash registers */
464 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
465 if (retval
!= ERROR_OK
)
467 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
468 if (retval
!= ERROR_OK
)
471 for (i
= first
; i
<= last
; i
++) {
472 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
473 if (retval
!= ERROR_OK
)
475 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
476 bank
->base
+ bank
->sectors
[i
].offset
);
477 if (retval
!= ERROR_OK
)
479 retval
= target_write_u32(target
,
480 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
481 if (retval
!= ERROR_OK
)
484 retval
= stm32x_wait_status_busy(bank
, 100);
485 if (retval
!= ERROR_OK
)
488 bank
->sectors
[i
].is_erased
= 1;
491 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
492 if (retval
!= ERROR_OK
)
498 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
500 struct stm32x_flash_bank
*stm32x_info
= NULL
;
501 struct target
*target
= bank
->target
;
502 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
507 stm32x_info
= bank
->driver_priv
;
509 if (target
->state
!= TARGET_HALTED
) {
510 LOG_ERROR("Target not halted");
511 return ERROR_TARGET_NOT_HALTED
;
514 int retval
= stm32x_check_operation_supported(bank
);
515 if (ERROR_OK
!= retval
)
518 if ((first
% stm32x_info
->ppage_size
) != 0) {
519 LOG_WARNING("aligned start protect sector to a %d sector boundary",
520 stm32x_info
->ppage_size
);
521 first
= first
- (first
% stm32x_info
->ppage_size
);
523 if (((last
+ 1) % stm32x_info
->ppage_size
) != 0) {
524 LOG_WARNING("aligned end protect sector to a %d sector boundary",
525 stm32x_info
->ppage_size
);
527 last
= last
- (last
% stm32x_info
->ppage_size
);
531 /* medium density - each bit refers to a 4bank protection
532 * high density - each bit refers to a 2bank protection */
533 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
534 if (retval
!= ERROR_OK
)
537 prot_reg
[0] = (uint16_t)protection
;
538 prot_reg
[1] = (uint16_t)(protection
>> 8);
539 prot_reg
[2] = (uint16_t)(protection
>> 16);
540 prot_reg
[3] = (uint16_t)(protection
>> 24);
542 if (stm32x_info
->ppage_size
== 2) {
543 /* high density flash */
545 /* bit 7 controls sector 62 - 255 protection */
548 prot_reg
[3] &= ~(1 << 7);
550 prot_reg
[3] |= (1 << 7);
558 for (i
= first
; i
<= last
; i
++) {
559 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
560 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
563 prot_reg
[reg
] &= ~(1 << bit
);
565 prot_reg
[reg
] |= (1 << bit
);
568 /* medium density flash */
569 for (i
= first
; i
<= last
; i
++) {
570 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
571 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
574 prot_reg
[reg
] &= ~(1 << bit
);
576 prot_reg
[reg
] |= (1 << bit
);
580 status
= stm32x_erase_options(bank
);
581 if (status
!= ERROR_OK
)
584 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
585 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
586 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
587 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
589 return stm32x_write_options(bank
);
592 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
593 uint32_t offset
, uint32_t count
)
595 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
596 struct target
*target
= bank
->target
;
597 uint32_t buffer_size
= 16384;
598 struct working_area
*source
;
599 uint32_t address
= bank
->base
+ offset
;
600 struct reg_param reg_params
[5];
601 struct armv7m_algorithm armv7m_info
;
602 int retval
= ERROR_OK
;
604 /* see contrib/loaders/flash/stm32f1x.S for src */
606 static const uint8_t stm32x_flash_write_code
[] = {
607 /* #define STM32_FLASH_CR_OFFSET 0x10 */
608 /* #define STM32_FLASH_SR_OFFSET 0x0C */
610 0x16, 0x68, /* ldr r6, [r2, #0] */
611 0x00, 0x2e, /* cmp r6, #0 */
612 0x1a, 0xd0, /* beq exit */
613 0x55, 0x68, /* ldr r5, [r2, #4] */
614 0xb5, 0x42, /* cmp r5, r6 */
615 0xf9, 0xd0, /* beq wait_fifo */
616 0x01, 0x26, /* movs r6, #1 */
617 0x06, 0x61, /* str r6, [r0, #STM32_FLASH_CR_OFFSET] */
618 0x2e, 0x88, /* ldrh r6, [r5, #0] */
619 0x26, 0x80, /* strh r6, [r4, #0] */
620 0x02, 0x35, /* adds r5, #2 */
621 0x02, 0x34, /* adds r4, #2 */
623 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
624 0x01, 0x27, /* movs r7, #1 */
625 0x3e, 0x42, /* tst r6, r7 */
626 0xfb, 0xd1, /* bne busy */
627 0x14, 0x27, /* movs r7, #0x14 */
628 0x3e, 0x42, /* tst r6, r7 */
629 0x08, 0xd1, /* bne error */
630 0x9d, 0x42, /* cmp r5, r3 */
631 0x01, 0xd3, /* bcc no_wrap */
632 0x15, 0x46, /* mov r5, r2 */
633 0x08, 0x35, /* adds r5, #8 */
635 0x55, 0x60, /* str r5, [r2, #4] */
636 0x01, 0x39, /* subs r1, r1, #1 */
637 0x00, 0x29, /* cmp r1, #0 */
638 0x02, 0xd0, /* beq exit */
639 0xe3, 0xe7, /* b wait_fifo */
641 0x00, 0x20, /* movs r0, #0 */
642 0x50, 0x60, /* str r0, [r2, #4] */
644 0x30, 0x46, /* mov r0, r6 */
645 0x00, 0xbe, /* bkpt #0 */
648 /* flash write code */
649 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
650 &stm32x_info
->write_algorithm
) != ERROR_OK
) {
651 LOG_WARNING("no working area available, can't do block memory writes");
652 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
655 retval
= target_write_buffer(target
, stm32x_info
->write_algorithm
->address
,
656 sizeof(stm32x_flash_write_code
), (uint8_t *)stm32x_flash_write_code
);
657 if (retval
!= ERROR_OK
)
661 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
663 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
664 if (buffer_size
<= 256) {
665 /* if we already allocated the writing code, but failed to get a
666 * buffer, free the algorithm */
667 if (stm32x_info
->write_algorithm
)
668 target_free_working_area(target
, stm32x_info
->write_algorithm
);
670 LOG_WARNING("no large enough working area available, can't do block memory writes");
671 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
675 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
676 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
677 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
678 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
679 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
681 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
682 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
683 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
684 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
685 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
687 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
688 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
690 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
693 source
->address
, source
->size
,
694 stm32x_info
->write_algorithm
->address
, 0,
697 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
698 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
699 buf_get_u32(reg_params
[4].value
, 0, 32));
701 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
702 LOG_ERROR("flash memory not erased before writing");
703 /* Clear but report errors */
704 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
707 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
708 LOG_ERROR("flash memory write protected");
709 /* Clear but report errors */
710 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
714 target_free_working_area(target
, source
);
715 target_free_working_area(target
, stm32x_info
->write_algorithm
);
717 destroy_reg_param(®_params
[0]);
718 destroy_reg_param(®_params
[1]);
719 destroy_reg_param(®_params
[2]);
720 destroy_reg_param(®_params
[3]);
721 destroy_reg_param(®_params
[4]);
726 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
727 uint32_t offset
, uint32_t count
)
729 struct target
*target
= bank
->target
;
730 uint32_t words_remaining
= (count
/ 2);
731 uint32_t bytes_remaining
= (count
& 0x00000001);
732 uint32_t address
= bank
->base
+ offset
;
733 uint32_t bytes_written
= 0;
736 if (bank
->target
->state
!= TARGET_HALTED
) {
737 LOG_ERROR("Target not halted");
738 return ERROR_TARGET_NOT_HALTED
;
742 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
743 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
746 /* unlock flash registers */
747 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
748 if (retval
!= ERROR_OK
)
750 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
751 if (retval
!= ERROR_OK
)
754 /* multiple half words (2-byte) to be programmed? */
755 if (words_remaining
> 0) {
756 /* try using a block write */
757 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
758 if (retval
!= ERROR_OK
) {
759 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
760 /* if block write failed (no sufficient working area),
761 * we use normal (slow) single dword accesses */
762 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
765 buffer
+= words_remaining
* 2;
766 address
+= words_remaining
* 2;
771 if ((retval
!= ERROR_OK
) && (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
))
774 while (words_remaining
> 0) {
776 memcpy(&value
, buffer
+ bytes_written
, sizeof(uint16_t));
778 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
779 if (retval
!= ERROR_OK
)
781 retval
= target_write_u16(target
, address
, value
);
782 if (retval
!= ERROR_OK
)
785 retval
= stm32x_wait_status_busy(bank
, 5);
786 if (retval
!= ERROR_OK
)
794 if (bytes_remaining
) {
795 uint16_t value
= 0xffff;
796 memcpy(&value
, buffer
+ bytes_written
, bytes_remaining
);
798 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
799 if (retval
!= ERROR_OK
)
801 retval
= target_write_u16(target
, address
, value
);
802 if (retval
!= ERROR_OK
)
805 retval
= stm32x_wait_status_busy(bank
, 5);
806 if (retval
!= ERROR_OK
)
810 return target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
813 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
815 /* This check the device CPUID core register to detect
816 * the M0 from the M3 devices. */
818 struct target
*target
= bank
->target
;
819 uint32_t cpuid
, device_id_register
= 0;
821 /* Get the CPUID from the ARM Core
822 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
823 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
824 if (retval
!= ERROR_OK
)
827 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
828 /* 0xC20 is M0 devices */
829 device_id_register
= 0x40015800;
830 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
831 /* 0xC23 is M3 devices */
832 device_id_register
= 0xE0042000;
834 LOG_ERROR("Cannot identify target as a stm32x");
838 /* read stm32 device id register */
839 retval
= target_read_u32(target
, device_id_register
, device_id
);
840 if (retval
!= ERROR_OK
)
846 static int stm32x_probe(struct flash_bank
*bank
)
848 struct target
*target
= bank
->target
;
849 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
851 uint16_t flash_size_in_kb
;
854 uint32_t base_address
= 0x08000000;
857 stm32x_info
->probed
= 0;
858 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
860 /* read stm32 device id register */
861 int retval
= stm32x_get_device_id(bank
, &device_id
);
862 if (retval
!= ERROR_OK
)
865 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
867 /* get flash size from target. */
868 retval
= target_read_u16(target
, 0x1FFFF7E0, &flash_size_in_kb
);
869 if (retval
!= ERROR_OK
) {
870 LOG_WARNING("failed reading flash size, default to max target family");
871 /* failed reading flash size, default to max target family */
872 flash_size_in_kb
= 0xffff;
875 if ((device_id
& 0xfff) == 0x410) {
876 /* medium density - we have 1k pages
877 * 4 pages for a protection area */
879 stm32x_info
->ppage_size
= 4;
881 /* check for early silicon */
882 if (flash_size_in_kb
== 0xffff) {
883 /* number of sectors incorrect on revA */
884 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
885 flash_size_in_kb
= 128;
887 } else if ((device_id
& 0xfff) == 0x412) {
888 /* low density - we have 1k pages
889 * 4 pages for a protection area */
891 stm32x_info
->ppage_size
= 4;
893 /* check for early silicon */
894 if (flash_size_in_kb
== 0xffff) {
895 /* number of sectors incorrect on revA */
896 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
897 flash_size_in_kb
= 32;
899 } else if ((device_id
& 0xfff) == 0x414) {
900 /* high density - we have 2k pages
901 * 2 pages for a protection area */
903 stm32x_info
->ppage_size
= 2;
905 /* check for early silicon */
906 if (flash_size_in_kb
== 0xffff) {
907 /* number of sectors incorrect on revZ */
908 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
909 flash_size_in_kb
= 512;
911 } else if ((device_id
& 0xfff) == 0x418) {
912 /* connectivity line density - we have 2k pages
913 * 2 pages for a protection area */
915 stm32x_info
->ppage_size
= 2;
917 /* check for early silicon */
918 if (flash_size_in_kb
== 0xffff) {
919 /* number of sectors incorrect on revZ */
920 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
921 flash_size_in_kb
= 256;
923 } else if ((device_id
& 0xfff) == 0x420) {
924 /* value line density - we have 1k pages
925 * 4 pages for a protection area */
927 stm32x_info
->ppage_size
= 4;
929 /* check for early silicon */
930 if (flash_size_in_kb
== 0xffff) {
931 /* number of sectors may be incorrrect on early silicon */
932 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
933 flash_size_in_kb
= 128;
935 } else if ((device_id
& 0xfff) == 0x428) {
936 /* value line High density - we have 2k pages
937 * 4 pages for a protection area */
939 stm32x_info
->ppage_size
= 4;
941 /* check for early silicon */
942 if (flash_size_in_kb
== 0xffff) {
943 /* number of sectors may be incorrrect on early silicon */
944 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
945 flash_size_in_kb
= 128;
947 } else if ((device_id
& 0xfff) == 0x430) {
948 /* xl line density - we have 2k pages
949 * 2 pages for a protection area */
951 stm32x_info
->ppage_size
= 2;
952 stm32x_info
->has_dual_banks
= true;
954 /* check for early silicon */
955 if (flash_size_in_kb
== 0xffff) {
956 /* number of sectors may be incorrrect on early silicon */
957 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
958 flash_size_in_kb
= 1024;
961 /* split reported size into matching bank */
962 if (bank
->base
!= 0x08080000) {
963 /* bank 0 will be fixed 512k */
964 flash_size_in_kb
= 512;
966 flash_size_in_kb
-= 512;
967 /* bank1 also uses a register offset */
968 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
969 base_address
= 0x08080000;
971 } else if ((device_id
& 0xfff) == 0x440) {
972 /* stm32f0x - we have 1k pages
973 * 4 pages for a protection area */
975 stm32x_info
->ppage_size
= 4;
977 /* check for early silicon */
978 if (flash_size_in_kb
== 0xffff) {
979 /* number of sectors incorrect on revZ */
980 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 64k flash");
981 flash_size_in_kb
= 64;
984 LOG_WARNING("Cannot identify target as a STM32 family.");
988 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
990 /* did we assign flash size? */
991 assert(flash_size_in_kb
!= 0xffff);
993 /* calculate numbers of pages */
994 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
996 /* check that calculation result makes sense */
997 assert(num_pages
> 0);
1000 free(bank
->sectors
);
1001 bank
->sectors
= NULL
;
1004 bank
->base
= base_address
;
1005 bank
->size
= (num_pages
* page_size
);
1006 bank
->num_sectors
= num_pages
;
1007 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
1009 for (i
= 0; i
< num_pages
; i
++) {
1010 bank
->sectors
[i
].offset
= i
* page_size
;
1011 bank
->sectors
[i
].size
= page_size
;
1012 bank
->sectors
[i
].is_erased
= -1;
1013 bank
->sectors
[i
].is_protected
= 1;
1016 stm32x_info
->probed
= 1;
1021 static int stm32x_auto_probe(struct flash_bank
*bank
)
1023 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1024 if (stm32x_info
->probed
)
1026 return stm32x_probe(bank
);
1030 COMMAND_HANDLER(stm32x_handle_part_id_command
)
1036 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1041 /* read stm32 device id register */
1042 int retval
= stm32x_get_device_id(bank
, &device_id
);
1043 if (retval
!= ERROR_OK
)
1046 if ((device_id
& 0xfff) == 0x410) {
1047 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
1049 buf_size
-= printed
;
1051 switch (device_id
>> 16) {
1053 snprintf(buf
, buf_size
, "A");
1057 snprintf(buf
, buf_size
, "B");
1061 snprintf(buf
, buf_size
, "Z");
1065 snprintf(buf
, buf_size
, "Y");
1069 snprintf(buf
, buf_size
, "unknown");
1072 } else if ((device_id
& 0xfff) == 0x412) {
1073 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
1075 buf_size
-= printed
;
1077 switch (device_id
>> 16) {
1079 snprintf(buf
, buf_size
, "A");
1083 snprintf(buf
, buf_size
, "unknown");
1086 } else if ((device_id
& 0xfff) == 0x414) {
1087 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
1089 buf_size
-= printed
;
1091 switch (device_id
>> 16) {
1093 snprintf(buf
, buf_size
, "A");
1097 snprintf(buf
, buf_size
, "Z");
1101 snprintf(buf
, buf_size
, "unknown");
1104 } else if ((device_id
& 0xfff) == 0x418) {
1105 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
1107 buf_size
-= printed
;
1109 switch (device_id
>> 16) {
1111 snprintf(buf
, buf_size
, "A");
1115 snprintf(buf
, buf_size
, "Z");
1119 snprintf(buf
, buf_size
, "unknown");
1122 } else if ((device_id
& 0xfff) == 0x420) {
1123 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
1125 buf_size
-= printed
;
1127 switch (device_id
>> 16) {
1129 snprintf(buf
, buf_size
, "A");
1133 snprintf(buf
, buf_size
, "Z");
1137 snprintf(buf
, buf_size
, "unknown");
1140 } else if ((device_id
& 0xfff) == 0x428) {
1141 printed
= snprintf(buf
, buf_size
, "stm32x (Value HD) - Rev: ");
1143 buf_size
-= printed
;
1145 switch (device_id
>> 16) {
1147 snprintf(buf
, buf_size
, "A");
1151 snprintf(buf
, buf_size
, "Z");
1155 snprintf(buf
, buf_size
, "unknown");
1158 } else if ((device_id
& 0xfff) == 0x430) {
1159 printed
= snprintf(buf
, buf_size
, "stm32x (XL) - Rev: ");
1161 buf_size
-= printed
;
1163 switch (device_id
>> 16) {
1165 snprintf(buf
, buf_size
, "A");
1169 snprintf(buf
, buf_size
, "unknown");
1172 } else if ((device_id
& 0xfff) == 0x440) {
1173 printed
= snprintf(buf
, buf_size
, "stm32f0x - Rev: ");
1175 buf_size
-= printed
;
1177 switch (device_id
>> 16) {
1179 snprintf(buf
, buf_size
, "1.0");
1183 snprintf(buf
, buf_size
, "2.0");
1187 snprintf(buf
, buf_size
, "unknown");
1191 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
1198 COMMAND_HANDLER(stm32x_handle_lock_command
)
1200 struct target
*target
= NULL
;
1201 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1204 return ERROR_COMMAND_SYNTAX_ERROR
;
1206 struct flash_bank
*bank
;
1207 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1208 if (ERROR_OK
!= retval
)
1211 stm32x_info
= bank
->driver_priv
;
1213 target
= bank
->target
;
1215 if (target
->state
!= TARGET_HALTED
) {
1216 LOG_ERROR("Target not halted");
1217 return ERROR_TARGET_NOT_HALTED
;
1220 retval
= stm32x_check_operation_supported(bank
);
1221 if (ERROR_OK
!= retval
)
1224 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1225 command_print(CMD_CTX
, "stm32x failed to erase options");
1229 /* set readout protection */
1230 stm32x_info
->option_bytes
.RDP
= 0;
1232 if (stm32x_write_options(bank
) != ERROR_OK
) {
1233 command_print(CMD_CTX
, "stm32x failed to lock device");
1237 command_print(CMD_CTX
, "stm32x locked");
1242 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1244 struct target
*target
= NULL
;
1247 return ERROR_COMMAND_SYNTAX_ERROR
;
1249 struct flash_bank
*bank
;
1250 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1251 if (ERROR_OK
!= retval
)
1254 target
= bank
->target
;
1256 if (target
->state
!= TARGET_HALTED
) {
1257 LOG_ERROR("Target not halted");
1258 return ERROR_TARGET_NOT_HALTED
;
1261 retval
= stm32x_check_operation_supported(bank
);
1262 if (ERROR_OK
!= retval
)
1265 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1266 command_print(CMD_CTX
, "stm32x failed to unlock device");
1270 if (stm32x_write_options(bank
) != ERROR_OK
) {
1271 command_print(CMD_CTX
, "stm32x failed to lock device");
1275 command_print(CMD_CTX
, "stm32x unlocked.\n"
1276 "INFO: a reset or power cycle is required "
1277 "for the new settings to take effect.");
1282 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1284 uint32_t optionbyte
;
1285 struct target
*target
= NULL
;
1286 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1289 return ERROR_COMMAND_SYNTAX_ERROR
;
1291 struct flash_bank
*bank
;
1292 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1293 if (ERROR_OK
!= retval
)
1296 stm32x_info
= bank
->driver_priv
;
1298 target
= bank
->target
;
1300 if (target
->state
!= TARGET_HALTED
) {
1301 LOG_ERROR("Target not halted");
1302 return ERROR_TARGET_NOT_HALTED
;
1305 retval
= stm32x_check_operation_supported(bank
);
1306 if (ERROR_OK
!= retval
)
1309 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1310 if (retval
!= ERROR_OK
)
1312 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1314 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_ERROR
, 1))
1315 command_print(CMD_CTX
, "Option Byte Complement Error");
1317 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_READOUT
, 1))
1318 command_print(CMD_CTX
, "Readout Protection On");
1320 command_print(CMD_CTX
, "Readout Protection Off");
1322 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDWDGSW
, 1))
1323 command_print(CMD_CTX
, "Software Watchdog");
1325 command_print(CMD_CTX
, "Hardware Watchdog");
1327 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTOP
, 1))
1328 command_print(CMD_CTX
, "Stop: No reset generated");
1330 command_print(CMD_CTX
, "Stop: Reset generated");
1332 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1333 command_print(CMD_CTX
, "Standby: No reset generated");
1335 command_print(CMD_CTX
, "Standby: Reset generated");
1337 if (stm32x_info
->has_dual_banks
) {
1338 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_BFB2
, 1))
1339 command_print(CMD_CTX
, "Boot: Bank 0");
1341 command_print(CMD_CTX
, "Boot: Bank 1");
1347 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1349 struct target
*target
= NULL
;
1350 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1351 uint16_t optionbyte
= 0xF8;
1354 return ERROR_COMMAND_SYNTAX_ERROR
;
1356 struct flash_bank
*bank
;
1357 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1358 if (ERROR_OK
!= retval
)
1361 stm32x_info
= bank
->driver_priv
;
1363 target
= bank
->target
;
1365 if (target
->state
!= TARGET_HALTED
) {
1366 LOG_ERROR("Target not halted");
1367 return ERROR_TARGET_NOT_HALTED
;
1370 retval
= stm32x_check_operation_supported(bank
);
1371 if (ERROR_OK
!= retval
)
1374 /* REVISIT: ignores some options which we will display...
1375 * and doesn't insist on the specified syntax.
1379 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1380 optionbyte
|= (1 << 0);
1381 else /* REVISIT must be "HWWDG" then ... */
1382 optionbyte
&= ~(1 << 0);
1385 if (strcmp(CMD_ARGV
[2], "NORSTSTOP") == 0)
1386 optionbyte
|= (1 << 1);
1387 else /* REVISIT must be "RSTSTNDBY" then ... */
1388 optionbyte
&= ~(1 << 1);
1390 /* OPT_RDRSTSTDBY */
1391 if (strcmp(CMD_ARGV
[3], "NORSTSTNDBY") == 0)
1392 optionbyte
|= (1 << 2);
1393 else /* REVISIT must be "RSTSTOP" then ... */
1394 optionbyte
&= ~(1 << 2);
1396 if (CMD_ARGC
> 4 && stm32x_info
->has_dual_banks
) {
1398 if (strcmp(CMD_ARGV
[4], "BOOT0") == 0)
1399 optionbyte
|= (1 << 3);
1401 optionbyte
&= ~(1 << 3);
1404 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1405 command_print(CMD_CTX
, "stm32x failed to erase options");
1409 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1411 if (stm32x_write_options(bank
) != ERROR_OK
) {
1412 command_print(CMD_CTX
, "stm32x failed to write options");
1416 command_print(CMD_CTX
, "stm32x write options complete.\n"
1417 "INFO: a reset or power cycle is required "
1418 "for the new settings to take effect.");
1423 static int stm32x_mass_erase(struct flash_bank
*bank
)
1425 struct target
*target
= bank
->target
;
1427 if (target
->state
!= TARGET_HALTED
) {
1428 LOG_ERROR("Target not halted");
1429 return ERROR_TARGET_NOT_HALTED
;
1432 /* unlock option flash registers */
1433 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1434 if (retval
!= ERROR_OK
)
1436 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1437 if (retval
!= ERROR_OK
)
1440 /* mass erase flash memory */
1441 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1442 if (retval
!= ERROR_OK
)
1444 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1445 FLASH_MER
| FLASH_STRT
);
1446 if (retval
!= ERROR_OK
)
1449 retval
= stm32x_wait_status_busy(bank
, 100);
1450 if (retval
!= ERROR_OK
)
1453 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1454 if (retval
!= ERROR_OK
)
1460 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1465 return ERROR_COMMAND_SYNTAX_ERROR
;
1467 struct flash_bank
*bank
;
1468 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1469 if (ERROR_OK
!= retval
)
1472 retval
= stm32x_mass_erase(bank
);
1473 if (retval
== ERROR_OK
) {
1474 /* set all sectors as erased */
1475 for (i
= 0; i
< bank
->num_sectors
; i
++)
1476 bank
->sectors
[i
].is_erased
= 1;
1478 command_print(CMD_CTX
, "stm32x mass erase complete");
1480 command_print(CMD_CTX
, "stm32x mass erase failed");
1485 static const struct command_registration stm32x_exec_command_handlers
[] = {
1488 .handler
= stm32x_handle_lock_command
,
1489 .mode
= COMMAND_EXEC
,
1491 .help
= "Lock entire flash device.",
1495 .handler
= stm32x_handle_unlock_command
,
1496 .mode
= COMMAND_EXEC
,
1498 .help
= "Unlock entire protected flash device.",
1501 .name
= "mass_erase",
1502 .handler
= stm32x_handle_mass_erase_command
,
1503 .mode
= COMMAND_EXEC
,
1505 .help
= "Erase entire flash device.",
1508 .name
= "options_read",
1509 .handler
= stm32x_handle_options_read_command
,
1510 .mode
= COMMAND_EXEC
,
1512 .help
= "Read and display device option byte.",
1515 .name
= "options_write",
1516 .handler
= stm32x_handle_options_write_command
,
1517 .mode
= COMMAND_EXEC
,
1518 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1519 "('RSTSTNDBY'|'NORSTSTNDBY') "
1520 "('RSTSTOP'|'NORSTSTOP')",
1521 .help
= "Replace bits in device option byte.",
1523 COMMAND_REGISTRATION_DONE
1526 static const struct command_registration stm32x_command_handlers
[] = {
1529 .mode
= COMMAND_ANY
,
1530 .help
= "stm32f1x flash command group",
1532 .chain
= stm32x_exec_command_handlers
,
1534 COMMAND_REGISTRATION_DONE
1537 struct flash_driver stm32f1x_flash
= {
1539 .commands
= stm32x_command_handlers
,
1540 .flash_bank_command
= stm32x_flash_bank_command
,
1541 .erase
= stm32x_erase
,
1542 .protect
= stm32x_protect
,
1543 .write
= stm32x_write
,
1544 .read
= default_flash_read
,
1545 .probe
= stm32x_probe
,
1546 .auto_probe
= stm32x_auto_probe
,
1547 .erase_check
= default_flash_mem_blank_check
,
1548 .protect_check
= stm32x_protect_check
,
1549 .info
= get_stm32x_info
,
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