1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 /* 2014-12: Addition of the SWD protocol support is based on the initial work
23 * by Paul Fertser and modifications by Jean-Christian de Rivaz. */
30 #include <jtag/interface.h>
31 #include <jtag/commands.h>
34 * Function bitbang_stableclocks
35 * issues a number of clock cycles while staying in a stable state.
36 * Because the TMS value required to stay in the RESET state is a 1, whereas
37 * the TMS value required to stay in any of the other stable states is a 0,
38 * this function checks the current stable state to decide on the value of TMS
41 static int bitbang_stableclocks(int num_cycles
);
43 static void bitbang_swd_write_reg(uint8_t cmd
, uint32_t value
, uint32_t ap_delay_clk
);
45 struct bitbang_interface
*bitbang_interface
;
47 /* DANGER!!!! clock absolutely *MUST* be 0 in idle or reset won't work!
49 * Set this to 1 and str912 reset halt will fail.
51 * If someone can submit a patch with an explanation it will be greatly
52 * appreciated, but as far as I can tell (ØH) DCLK is generated upon
53 * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation!
54 * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE
55 * state". With hardware there is no such thing as *while* in a state. There
56 * are only edges. So clk => 0 is in fact a very subtle state transition that
57 * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#&
59 * For "reset halt" the last thing that happens before srst is asserted
60 * is that the breakpoint is set up. If DCLK is not wiggled one last
61 * time before the reset, then the breakpoint is not set up and
62 * "reset halt" will fail to halt.
65 #define CLOCK_IDLE() 0
67 /* The bitbang driver leaves the TCK 0 when in idle */
68 static void bitbang_end_state(tap_state_t state
)
70 assert(tap_is_state_stable(state
));
71 tap_set_end_state(state
);
74 static int bitbang_state_move(int skip
)
77 uint8_t tms_scan
= tap_get_tms_path(tap_get_state(), tap_get_end_state());
78 int tms_count
= tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
80 for (i
= skip
; i
< tms_count
; i
++) {
81 tms
= (tms_scan
>> i
) & 1;
82 if (bitbang_interface
->write(0, tms
, 0) != ERROR_OK
)
84 if (bitbang_interface
->write(1, tms
, 0) != ERROR_OK
)
87 if (bitbang_interface
->write(CLOCK_IDLE(), tms
, 0) != ERROR_OK
)
90 tap_set_state(tap_get_end_state());
95 * Clock a bunch of TMS (or SWDIO) transitions, to change the JTAG
96 * (or SWD) state machine.
98 static int bitbang_execute_tms(struct jtag_command
*cmd
)
100 unsigned num_bits
= cmd
->cmd
.tms
->num_bits
;
101 const uint8_t *bits
= cmd
->cmd
.tms
->bits
;
103 LOG_DEBUG_IO("TMS: %d bits", num_bits
);
106 for (unsigned i
= 0; i
< num_bits
; i
++) {
107 tms
= ((bits
[i
/8] >> (i
% 8)) & 1);
108 if (bitbang_interface
->write(0, tms
, 0) != ERROR_OK
)
110 if (bitbang_interface
->write(1, tms
, 0) != ERROR_OK
)
113 if (bitbang_interface
->write(CLOCK_IDLE(), tms
, 0) != ERROR_OK
)
119 static int bitbang_path_move(struct pathmove_command
*cmd
)
121 int num_states
= cmd
->num_states
;
127 if (tap_state_transition(tap_get_state(), false) == cmd
->path
[state_count
])
129 else if (tap_state_transition(tap_get_state(), true) == cmd
->path
[state_count
])
132 LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
133 tap_state_name(tap_get_state()),
134 tap_state_name(cmd
->path
[state_count
]));
138 if (bitbang_interface
->write(0, tms
, 0) != ERROR_OK
)
140 if (bitbang_interface
->write(1, tms
, 0) != ERROR_OK
)
143 tap_set_state(cmd
->path
[state_count
]);
148 if (bitbang_interface
->write(CLOCK_IDLE(), tms
, 0) != ERROR_OK
)
151 tap_set_end_state(tap_get_state());
155 static int bitbang_runtest(int num_cycles
)
159 tap_state_t saved_end_state
= tap_get_end_state();
161 /* only do a state_move when we're not already in IDLE */
162 if (tap_get_state() != TAP_IDLE
) {
163 bitbang_end_state(TAP_IDLE
);
164 if (bitbang_state_move(0) != ERROR_OK
)
168 /* execute num_cycles */
169 for (i
= 0; i
< num_cycles
; i
++) {
170 if (bitbang_interface
->write(0, 0, 0) != ERROR_OK
)
172 if (bitbang_interface
->write(1, 0, 0) != ERROR_OK
)
175 if (bitbang_interface
->write(CLOCK_IDLE(), 0, 0) != ERROR_OK
)
178 /* finish in end_state */
179 bitbang_end_state(saved_end_state
);
180 if (tap_get_state() != tap_get_end_state())
181 if (bitbang_state_move(0) != ERROR_OK
)
187 static int bitbang_stableclocks(int num_cycles
)
189 int tms
= (tap_get_state() == TAP_RESET
? 1 : 0);
192 /* send num_cycles clocks onto the cable */
193 for (i
= 0; i
< num_cycles
; i
++) {
194 if (bitbang_interface
->write(1, tms
, 0) != ERROR_OK
)
196 if (bitbang_interface
->write(0, tms
, 0) != ERROR_OK
)
203 static int bitbang_scan(bool ir_scan
, enum scan_type type
, uint8_t *buffer
,
206 tap_state_t saved_end_state
= tap_get_end_state();
210 (tap_get_state() == TAP_DRSHIFT
)) ||
211 (ir_scan
&& (tap_get_state() == TAP_IRSHIFT
)))) {
213 bitbang_end_state(TAP_IRSHIFT
);
215 bitbang_end_state(TAP_DRSHIFT
);
217 if (bitbang_state_move(0) != ERROR_OK
)
219 bitbang_end_state(saved_end_state
);
223 for (bit_cnt
= 0; bit_cnt
< scan_size
; bit_cnt
++) {
224 int tms
= (bit_cnt
== scan_size
-1) ? 1 : 0;
226 int bytec
= bit_cnt
/8;
227 int bcval
= 1 << (bit_cnt
% 8);
229 /* if we're just reading the scan, but don't care about the output
230 * default to outputting 'low', this also makes valgrind traces more readable,
231 * as it removes the dependency on an uninitialised value
234 if ((type
!= SCAN_IN
) && (buffer
[bytec
] & bcval
))
237 if (bitbang_interface
->write(0, tms
, tdi
) != ERROR_OK
)
240 if (type
!= SCAN_OUT
) {
241 if (bitbang_interface
->buf_size
) {
242 if (bitbang_interface
->sample() != ERROR_OK
)
246 switch (bitbang_interface
->read()) {
248 buffer
[bytec
] &= ~bcval
;
251 buffer
[bytec
] |= bcval
;
259 if (bitbang_interface
->write(1, tms
, tdi
) != ERROR_OK
)
262 if (type
!= SCAN_OUT
&& bitbang_interface
->buf_size
&&
263 (buffered
== bitbang_interface
->buf_size
||
264 bit_cnt
== scan_size
- 1)) {
265 for (unsigned i
= bit_cnt
+ 1 - buffered
; i
<= bit_cnt
; i
++) {
266 switch (bitbang_interface
->read_sample()) {
268 buffer
[i
/8] &= ~(1 << (i
% 8));
271 buffer
[i
/8] |= 1 << (i
% 8);
281 if (tap_get_state() != tap_get_end_state()) {
282 /* we *KNOW* the above loop transitioned out of
283 * the shift state, so we skip the first state
284 * and move directly to the end state.
286 if (bitbang_state_move(1) != ERROR_OK
)
292 int bitbang_execute_queue(void)
294 struct jtag_command
*cmd
= jtag_command_queue
; /* currently processed command */
300 if (!bitbang_interface
) {
301 LOG_ERROR("BUG: Bitbang interface called, but not yet initialized");
305 /* return ERROR_OK, unless a jtag_read_buffer returns a failed check
306 * that wasn't handled by a caller-provided error handler
310 if (bitbang_interface
->blink
) {
311 if (bitbang_interface
->blink(1) != ERROR_OK
)
318 LOG_DEBUG_IO("runtest %i cycles, end in %s",
319 cmd
->cmd
.runtest
->num_cycles
,
320 tap_state_name(cmd
->cmd
.runtest
->end_state
));
321 bitbang_end_state(cmd
->cmd
.runtest
->end_state
);
322 if (bitbang_runtest(cmd
->cmd
.runtest
->num_cycles
) != ERROR_OK
)
326 case JTAG_STABLECLOCKS
:
327 /* this is only allowed while in a stable state. A check for a stable
328 * state was done in jtag_add_clocks()
330 if (bitbang_stableclocks(cmd
->cmd
.stableclocks
->num_cycles
) != ERROR_OK
)
335 LOG_DEBUG_IO("statemove end in %s",
336 tap_state_name(cmd
->cmd
.statemove
->end_state
));
337 bitbang_end_state(cmd
->cmd
.statemove
->end_state
);
338 if (bitbang_state_move(0) != ERROR_OK
)
342 LOG_DEBUG_IO("pathmove: %i states, end in %s",
343 cmd
->cmd
.pathmove
->num_states
,
344 tap_state_name(cmd
->cmd
.pathmove
->path
[cmd
->cmd
.pathmove
->num_states
- 1]));
345 if (bitbang_path_move(cmd
->cmd
.pathmove
) != ERROR_OK
)
349 bitbang_end_state(cmd
->cmd
.scan
->end_state
);
350 scan_size
= jtag_build_buffer(cmd
->cmd
.scan
, &buffer
);
351 LOG_DEBUG_IO("%s scan %d bits; end in %s",
352 (cmd
->cmd
.scan
->ir_scan
) ? "IR" : "DR",
354 tap_state_name(cmd
->cmd
.scan
->end_state
));
355 type
= jtag_scan_type(cmd
->cmd
.scan
);
356 if (bitbang_scan(cmd
->cmd
.scan
->ir_scan
, type
, buffer
,
357 scan_size
) != ERROR_OK
)
359 if (jtag_read_buffer(buffer
, cmd
->cmd
.scan
) != ERROR_OK
)
360 retval
= ERROR_JTAG_QUEUE_FAILED
;
364 LOG_DEBUG_IO("sleep %" PRIu32
, cmd
->cmd
.sleep
->us
);
365 jtag_sleep(cmd
->cmd
.sleep
->us
);
368 retval
= bitbang_execute_tms(cmd
);
371 LOG_ERROR("BUG: unknown JTAG command type encountered");
376 if (bitbang_interface
->blink
) {
377 if (bitbang_interface
->blink(0) != ERROR_OK
)
384 static int queued_retval
;
386 static int bitbang_swd_init(void)
388 LOG_DEBUG("bitbang_swd_init");
392 static void bitbang_swd_exchange(bool rnw
, uint8_t buf
[], unsigned int offset
, unsigned int bit_cnt
)
394 LOG_DEBUG("bitbang_swd_exchange");
396 if (bitbang_interface
->blink
) {
397 /* FIXME: we should manage errors */
398 bitbang_interface
->blink(1);
401 for (unsigned int i
= offset
; i
< bit_cnt
+ offset
; i
++) {
403 int bcval
= 1 << (i
% 8);
404 int swdio
= !rnw
&& (buf
[bytec
] & bcval
);
406 bitbang_interface
->swd_write(0, swdio
);
409 if (bitbang_interface
->swdio_read())
412 buf
[bytec
] &= ~bcval
;
415 bitbang_interface
->swd_write(1, swdio
);
418 if (bitbang_interface
->blink
) {
419 /* FIXME: we should manage errors */
420 bitbang_interface
->blink(0);
424 static int bitbang_swd_switch_seq(enum swd_special_seq seq
)
426 LOG_DEBUG("bitbang_swd_switch_seq");
430 LOG_DEBUG("SWD line reset");
431 bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset
, 0, swd_seq_line_reset_len
);
434 LOG_DEBUG("JTAG-to-SWD");
435 bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_swd
, 0, swd_seq_jtag_to_swd_len
);
438 LOG_DEBUG("SWD-to-JTAG");
439 bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_jtag
, 0, swd_seq_swd_to_jtag_len
);
442 LOG_ERROR("Sequence %d not supported", seq
);
449 static void swd_clear_sticky_errors(void)
451 bitbang_swd_write_reg(swd_cmd(false, false, DP_ABORT
),
452 STKCMPCLR
| STKERRCLR
| WDERRCLR
| ORUNERRCLR
, 0);
455 static void bitbang_swd_read_reg(uint8_t cmd
, uint32_t *value
, uint32_t ap_delay_clk
)
457 LOG_DEBUG("bitbang_swd_read_reg");
458 assert(cmd
& SWD_CMD_RnW
);
460 if (queued_retval
!= ERROR_OK
) {
461 LOG_DEBUG("Skip bitbang_swd_read_reg because queued_retval=%d", queued_retval
);
466 uint8_t trn_ack_data_parity_trn
[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
468 cmd
|= SWD_CMD_START
| (1 << 7);
469 bitbang_swd_exchange(false, &cmd
, 0, 8);
471 bitbang_interface
->swdio_drive(false);
472 bitbang_swd_exchange(true, trn_ack_data_parity_trn
, 0, 1 + 3 + 32 + 1 + 1);
473 bitbang_interface
->swdio_drive(true);
475 int ack
= buf_get_u32(trn_ack_data_parity_trn
, 1, 3);
476 uint32_t data
= buf_get_u32(trn_ack_data_parity_trn
, 1 + 3, 32);
477 int parity
= buf_get_u32(trn_ack_data_parity_trn
, 1 + 3 + 32, 1);
479 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32
,
480 ack
== SWD_ACK_OK
? "OK" : ack
== SWD_ACK_WAIT
? "WAIT" : ack
== SWD_ACK_FAULT
? "FAULT" : "JUNK",
481 cmd
& SWD_CMD_APnDP
? "AP" : "DP",
482 cmd
& SWD_CMD_RnW
? "read" : "write",
483 (cmd
& SWD_CMD_A32
) >> 1,
488 if (parity
!= parity_u32(data
)) {
489 LOG_DEBUG("Wrong parity detected");
490 queued_retval
= ERROR_FAIL
;
495 if (cmd
& SWD_CMD_APnDP
)
496 bitbang_swd_exchange(true, NULL
, 0, ap_delay_clk
);
499 LOG_DEBUG("SWD_ACK_WAIT");
500 swd_clear_sticky_errors();
503 LOG_DEBUG("SWD_ACK_FAULT");
507 LOG_DEBUG("No valid acknowledge: ack=%d", ack
);
514 static void bitbang_swd_write_reg(uint8_t cmd
, uint32_t value
, uint32_t ap_delay_clk
)
516 LOG_DEBUG("bitbang_swd_write_reg");
517 assert(!(cmd
& SWD_CMD_RnW
));
519 if (queued_retval
!= ERROR_OK
) {
520 LOG_DEBUG("Skip bitbang_swd_write_reg because queued_retval=%d", queued_retval
);
525 uint8_t trn_ack_data_parity_trn
[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
526 buf_set_u32(trn_ack_data_parity_trn
, 1 + 3 + 1, 32, value
);
527 buf_set_u32(trn_ack_data_parity_trn
, 1 + 3 + 1 + 32, 1, parity_u32(value
));
529 cmd
|= SWD_CMD_START
| (1 << 7);
530 bitbang_swd_exchange(false, &cmd
, 0, 8);
532 bitbang_interface
->swdio_drive(false);
533 bitbang_swd_exchange(true, trn_ack_data_parity_trn
, 0, 1 + 3 + 1);
534 bitbang_interface
->swdio_drive(true);
535 bitbang_swd_exchange(false, trn_ack_data_parity_trn
, 1 + 3 + 1, 32 + 1);
537 int ack
= buf_get_u32(trn_ack_data_parity_trn
, 1, 3);
538 LOG_DEBUG("%s %s %s reg %X = %08"PRIx32
,
539 ack
== SWD_ACK_OK
? "OK" : ack
== SWD_ACK_WAIT
? "WAIT" : ack
== SWD_ACK_FAULT
? "FAULT" : "JUNK",
540 cmd
& SWD_CMD_APnDP
? "AP" : "DP",
541 cmd
& SWD_CMD_RnW
? "read" : "write",
542 (cmd
& SWD_CMD_A32
) >> 1,
543 buf_get_u32(trn_ack_data_parity_trn
, 1 + 3 + 1, 32));
547 if (cmd
& SWD_CMD_APnDP
)
548 bitbang_swd_exchange(true, NULL
, 0, ap_delay_clk
);
551 LOG_DEBUG("SWD_ACK_WAIT");
552 swd_clear_sticky_errors();
555 LOG_DEBUG("SWD_ACK_FAULT");
559 LOG_DEBUG("No valid acknowledge: ack=%d", ack
);
566 static int bitbang_swd_run_queue(void)
568 LOG_DEBUG("bitbang_swd_run_queue");
569 /* A transaction must be followed by another transaction or at least 8 idle cycles to
570 * ensure that data is clocked through the AP. */
571 bitbang_swd_exchange(true, NULL
, 0, 8);
573 int retval
= queued_retval
;
574 queued_retval
= ERROR_OK
;
575 LOG_DEBUG("SWD queue return value: %02x", retval
);
579 const struct swd_driver bitbang_swd
= {
580 .init
= bitbang_swd_init
,
581 .switch_seq
= bitbang_swd_switch_seq
,
582 .read_reg
= bitbang_swd_read_reg
,
583 .write_reg
= bitbang_swd_write_reg
,
584 .run
= bitbang_swd_run_queue
,
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