2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * Copyright (C) 2018 by Liviu Ionescu
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
28 #ifndef OPENOCD_TARGET_ARM_H
29 #define OPENOCD_TARGET_ARM_H
31 #include <helper/command.h>
36 * Holds the interface to ARM cores.
38 * At this writing, only "classic ARM" cores built on the ARMv4 register
39 * and mode model are supported. The Thumb2-only microcontroller profile
40 * support has not yet been integrated, affecting Cortex-M parts.
44 * Indicates what registers are in the ARM state core register set.
46 * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
47 * on for example ARM7TDMI cores.
48 * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
49 * three more registers are shadowed for "Secure Monitor" mode.
50 * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
51 * and also security extensions. Additional shadowed registers for
52 * "Secure Monitor" and "Hypervisor" modes.
53 * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
54 * which only shadows SP.
57 ARM_CORE_TYPE_STD
= -1,
58 ARM_CORE_TYPE_SEC_EXT
= 1,
59 ARM_CORE_TYPE_VIRT_EXT
,
60 ARM_CORE_TYPE_M_PROFILE
,
64 * Represent state of an ARM core.
66 * Most numbers match the five low bits of the *PSR registers on
67 * "classic ARM" processors, which build on the ARMv4 processor
68 * modes and register set.
70 * ARM_MODE_ANY is a magic value, often used as a wildcard.
72 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
73 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
85 ARM_MODE_1176_MON
= 28,
89 ARM_MODE_USER_THREAD
= 1,
103 /* VFPv3 internal register numbers mapping to d0:31 */
140 const char *arm_mode_name(unsigned psr_mode
);
141 bool is_arm_mode(unsigned psr_mode
);
143 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
152 /** ARM vector floating point enabled, if yes which version. */
153 enum arm_vfp_version
{
160 #define ARM_COMMON_MAGIC 0x0A450A45
163 * Represents a generic ARM core, with standard application registers.
165 * There are sixteen application registers (including PC, SP, LR) and a PSR.
166 * Cortex-M series cores do not support as many core states or shadowed
167 * registers as traditional ARM cores, and only support Thumb2 instructions.
171 struct reg_cache
*core_cache
;
173 /** Handle to the PC; valid in all core modes. */
176 /** Handle to the CPSR/xPSR; valid in all core modes. */
179 /** Handle to the SPSR; valid only in core modes with an SPSR. */
182 /** Support for arm_reg_current() */
185 /** Indicates what registers are in the ARM state core register set. */
186 enum arm_core_type core_type
;
188 /** Record the current core mode: SVC, USR, or some other mode. */
189 enum arm_mode core_mode
;
191 /** Record the current core state: ARM, Thumb, or otherwise. */
192 enum arm_state core_state
;
194 /** Flag reporting unavailability of the BKPT instruction. */
197 /** Flag reporting armv6m based core. */
200 /** Flag reporting armv8m based core. */
203 /** Floating point or VFP version, 0 if disabled. */
206 int (*setup_semihosting
)(struct target
*target
, int enable
);
208 /** Backpointer to the target. */
209 struct target
*target
;
211 /** Handle for the debug module, if one is present. */
214 /** Handle for the Embedded Trace Module, if one is present. */
215 struct etm_context
*etm
;
217 /* FIXME all these methods should take "struct arm *" not target */
219 /** Retrieve all core registers, for display. */
220 int (*full_context
)(struct target
*target
);
222 /** Retrieve a single core register. */
223 int (*read_core_reg
)(struct target
*target
, struct reg
*reg
,
224 int num
, enum arm_mode mode
);
225 int (*write_core_reg
)(struct target
*target
, struct reg
*reg
,
226 int num
, enum arm_mode mode
, uint8_t *value
);
228 /** Read coprocessor register. */
229 int (*mrc
)(struct target
*target
, int cpnum
,
230 uint32_t op1
, uint32_t op2
,
231 uint32_t CRn
, uint32_t CRm
,
234 /** Write coprocessor register. */
235 int (*mcr
)(struct target
*target
, int cpnum
,
236 uint32_t op1
, uint32_t op2
,
237 uint32_t CRn
, uint32_t CRm
,
242 /** For targets conforming to ARM Debug Interface v5,
243 * this handle references the Debug Access Port (DAP)
244 * used to make requests to the target.
246 struct adiv5_dap
*dap
;
249 /** Convert target handle to generic ARM target state handle. */
250 static inline struct arm
*target_to_arm(struct target
*target
)
252 assert(target
!= NULL
);
253 return target
->arch_info
;
256 static inline bool is_arm(struct arm
*arm
)
259 return arm
->common_magic
== ARM_COMMON_MAGIC
;
262 struct arm_algorithm
{
265 enum arm_mode core_mode
;
266 enum arm_state core_state
;
272 struct target
*target
;
277 struct reg_cache
*arm_build_reg_cache(struct target
*target
, struct arm
*arm
);
278 void arm_free_reg_cache(struct arm
*arm
);
280 struct reg_cache
*armv8_build_reg_cache(struct target
*target
);
282 extern const struct command_registration arm_command_handlers
[];
284 int arm_arch_state(struct target
*target
);
285 const char *arm_get_gdb_arch(struct target
*target
);
286 int arm_get_gdb_reg_list(struct target
*target
,
287 struct reg
**reg_list
[], int *reg_list_size
,
288 enum target_register_class reg_class
);
289 const char *armv8_get_gdb_arch(struct target
*target
);
290 int armv8_get_gdb_reg_list(struct target
*target
,
291 struct reg
**reg_list
[], int *reg_list_size
,
292 enum target_register_class reg_class
);
294 int arm_init_arch_info(struct target
*target
, struct arm
*arm
);
296 /* REVISIT rename this once it's usable by ARMv7-M */
297 int armv4_5_run_algorithm(struct target
*target
,
298 int num_mem_params
, struct mem_param
*mem_params
,
299 int num_reg_params
, struct reg_param
*reg_params
,
300 target_addr_t entry_point
, target_addr_t exit_point
,
301 int timeout_ms
, void *arch_info
);
302 int armv4_5_run_algorithm_inner(struct target
*target
,
303 int num_mem_params
, struct mem_param
*mem_params
,
304 int num_reg_params
, struct reg_param
*reg_params
,
305 uint32_t entry_point
, uint32_t exit_point
,
306 int timeout_ms
, void *arch_info
,
307 int (*run_it
)(struct target
*target
, uint32_t exit_point
,
308 int timeout_ms
, void *arch_info
));
310 int arm_checksum_memory(struct target
*target
,
311 target_addr_t address
, uint32_t count
, uint32_t *checksum
);
312 int arm_blank_check_memory(struct target
*target
,
313 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
);
315 void arm_set_cpsr(struct arm
*arm
, uint32_t cpsr
);
316 struct reg
*arm_reg_current(struct arm
*arm
, unsigned regnum
);
317 struct reg
*armv8_reg_current(struct arm
*arm
, unsigned regnum
);
319 extern struct reg arm_gdb_dummy_fp_reg
;
320 extern struct reg arm_gdb_dummy_fps_reg
;
322 #endif /* OPENOCD_TARGET_ARM_H */
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