1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
12 ***************************************************************************/
14 #ifndef OPENOCD_TARGET_ARMV7M_H
15 #define OPENOCD_TARGET_ARMV7M_H
18 #include "armv7m_trace.h"
22 extern const int armv7m_psp_reg_map
[];
23 extern const int armv7m_msp_reg_map
[];
25 const char *armv7m_exception_string(int number
);
27 /* Cortex-M DCRSR.REGSEL selectors */
47 ARMV7M_REGSEL_PC
= 15,
49 ARMV7M_REGSEL_XPSR
= 16,
53 ARMV8M_REGSEL_MSP_NS
= 0x18,
57 ARMV8M_REGSEL_MSPLIM_S
,
58 ARMV8M_REGSEL_PSPLIM_S
,
59 ARMV8M_REGSEL_MSPLIM_NS
,
60 ARMV8M_REGSEL_PSPLIM_NS
,
62 ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL
= 0x14,
63 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S
= 0x22,
64 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS
= 0x23,
65 ARMV7M_REGSEL_FPSCR
= 0x21,
67 /* 32bit Floating-point registers */
68 ARMV7M_REGSEL_S0
= 0x40,
102 /* offsets into armv7m core register cache */
104 /* for convenience, the first set of indices match
105 * the Cortex-M DCRSR.REGSEL selectors
107 ARMV7M_R0
= ARMV7M_REGSEL_R0
,
108 ARMV7M_R1
= ARMV7M_REGSEL_R1
,
109 ARMV7M_R2
= ARMV7M_REGSEL_R2
,
110 ARMV7M_R3
= ARMV7M_REGSEL_R3
,
112 ARMV7M_R4
= ARMV7M_REGSEL_R4
,
113 ARMV7M_R5
= ARMV7M_REGSEL_R5
,
114 ARMV7M_R6
= ARMV7M_REGSEL_R6
,
115 ARMV7M_R7
= ARMV7M_REGSEL_R7
,
117 ARMV7M_R8
= ARMV7M_REGSEL_R8
,
118 ARMV7M_R9
= ARMV7M_REGSEL_R9
,
119 ARMV7M_R10
= ARMV7M_REGSEL_R10
,
120 ARMV7M_R11
= ARMV7M_REGSEL_R11
,
122 ARMV7M_R12
= ARMV7M_REGSEL_R12
,
123 ARMV7M_R13
= ARMV7M_REGSEL_R13
,
124 ARMV7M_R14
= ARMV7M_REGSEL_R14
,
125 ARMV7M_PC
= ARMV7M_REGSEL_PC
,
127 ARMV7M_XPSR
= ARMV7M_REGSEL_XPSR
,
128 ARMV7M_MSP
= ARMV7M_REGSEL_MSP
,
129 ARMV7M_PSP
= ARMV7M_REGSEL_PSP
,
131 /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
133 /* A block of container and contained registers follows:
134 * THE ORDER IS IMPORTANT to the end of the block ! */
135 /* working register for packing/unpacking special regs, hidden from gdb */
136 ARMV7M_PMSK_BPRI_FLTMSK_CTRL
,
138 /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
139 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
140 * cache only and are not flushed to CPU HW register.
141 * To trigger write to CPU HW register, add
142 * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
148 /* The end of block of container and contained registers */
150 /* ARMv8-M specific registers */
160 /* A block of container and contained registers follows:
161 * THE ORDER IS IMPORTANT to the end of the block ! */
162 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S
,
167 /* The end of block of container and contained registers */
169 /* A block of container and contained registers follows:
170 * THE ORDER IS IMPORTANT to the end of the block ! */
171 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS
,
176 /* The end of block of container and contained registers */
178 /* 64bit Floating-point registers */
196 /* Floating-point status register */
199 /* for convenience add registers' block delimiters */
201 ARMV7M_CORE_FIRST_REG
= ARMV7M_R0
,
202 ARMV7M_CORE_LAST_REG
= ARMV7M_XPSR
,
203 ARMV7M_FPU_FIRST_REG
= ARMV7M_D0
,
204 ARMV7M_FPU_LAST_REG
= ARMV7M_FPSCR
,
205 ARMV8M_FIRST_REG
= ARMV8M_MSP_NS
,
206 ARMV8M_LAST_REG
= ARMV8M_CONTROL_NS
,
216 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
218 #define ARMV7M_COMMON_MAGIC 0x2A452A45U
220 struct armv7m_common
{
221 unsigned int common_magic
;
225 int exception_number
;
227 /* AP this processor is connected to in the DAP */
228 struct adiv5_ap
*debug_ap
;
233 /* hla_target uses a high level adapter that does not support all functions */
236 struct armv7m_trace_config trace_config
;
238 /* Direct processor core register read and writes */
239 int (*load_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t *value
);
240 int (*store_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t value
);
242 int (*examine_debug_reason
)(struct target
*target
);
243 int (*post_debug_entry
)(struct target
*target
);
245 void (*pre_restore_context
)(struct target
*target
);
248 static inline bool is_armv7m(const struct armv7m_common
*armv7m
)
250 return armv7m
->common_magic
== ARMV7M_COMMON_MAGIC
;
254 * @returns the pointer to the target specific struct
255 * without matching a magic number.
256 * Use in target specific service routines, where the correct
257 * type of arch_info is certain.
259 static inline struct armv7m_common
*
260 target_to_armv7m(struct target
*target
)
262 return container_of(target
->arch_info
, struct armv7m_common
, arm
);
266 * @returns the pointer to the target specific struct
267 * or NULL if the magic number does not match.
268 * Use in a flash driver or any place where mismatch of the arch_info
271 static inline struct armv7m_common
*
272 target_to_armv7m_safe(struct target
*target
)
277 if (!target
->arch_info
)
280 /* Check the parent type first to prevent peeking memory too far
281 * from arch_info pointer */
282 if (!is_arm(target_to_arm(target
)))
285 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
286 if (!is_armv7m(armv7m
))
292 struct armv7m_algorithm
{
293 unsigned int common_magic
;
295 enum arm_mode core_mode
;
297 uint32_t context
[ARMV7M_LAST_REG
]; /* ARMV7M_NUM_REGS */
300 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
);
301 void armv7m_free_reg_cache(struct target
*target
);
303 enum armv7m_mode
armv7m_number_to_mode(int number
);
304 int armv7m_mode_to_number(enum armv7m_mode mode
);
306 int armv7m_arch_state(struct target
*target
);
307 int armv7m_get_gdb_reg_list(struct target
*target
,
308 struct reg
**reg_list
[], int *reg_list_size
,
309 enum target_register_class reg_class
);
311 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
);
313 int armv7m_run_algorithm(struct target
*target
,
314 int num_mem_params
, struct mem_param
*mem_params
,
315 int num_reg_params
, struct reg_param
*reg_params
,
316 target_addr_t entry_point
, target_addr_t exit_point
,
317 int timeout_ms
, void *arch_info
);
319 int armv7m_start_algorithm(struct target
*target
,
320 int num_mem_params
, struct mem_param
*mem_params
,
321 int num_reg_params
, struct reg_param
*reg_params
,
322 target_addr_t entry_point
, target_addr_t exit_point
,
325 int armv7m_wait_algorithm(struct target
*target
,
326 int num_mem_params
, struct mem_param
*mem_params
,
327 int num_reg_params
, struct reg_param
*reg_params
,
328 target_addr_t exit_point
, int timeout_ms
,
331 int armv7m_invalidate_core_regs(struct target
*target
);
333 int armv7m_restore_context(struct target
*target
);
335 uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id
);
337 bool armv7m_map_reg_packing(unsigned int arm_reg_id
,
338 unsigned int *reg32_id
, uint32_t *offset
);
340 int armv7m_checksum_memory(struct target
*target
,
341 target_addr_t address
, uint32_t count
, uint32_t *checksum
);
342 int armv7m_blank_check_memory(struct target
*target
,
343 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
);
345 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
);
347 extern const struct command_registration armv7m_command_handlers
[];
349 #endif /* OPENOCD_TARGET_ARMV7M_H */
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