1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_ARMV7M_H
26 #define OPENOCD_TARGET_ARMV7M_H
29 #include "armv7m_trace.h"
33 extern const int armv7m_psp_reg_map
[];
34 extern const int armv7m_msp_reg_map
[];
36 const char *armv7m_exception_string(int number
);
38 /* Cortex-M DCRSR.REGSEL selectors */
58 ARMV7M_REGSEL_PC
= 15,
60 ARMV7M_REGSEL_xPSR
= 16,
64 ARMV8M_REGSEL_MSP_NS
= 0x18,
68 ARMV8M_REGSEL_MSPLIM_S
,
69 ARMV8M_REGSEL_PSPLIM_S
,
70 ARMV8M_REGSEL_MSPLIM_NS
,
71 ARMV8M_REGSEL_PSPLIM_NS
,
73 ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL
= 0x14,
74 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S
= 0x22,
75 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS
= 0x23,
76 ARMV7M_REGSEL_FPSCR
= 0x21,
78 /* 32bit Floating-point registers */
79 ARMV7M_REGSEL_S0
= 0x40,
113 /* offsets into armv7m core register cache */
115 /* for convenience, the first set of indices match
116 * the Cortex-M DCRSR.REGSEL selectors
118 ARMV7M_R0
= ARMV7M_REGSEL_R0
,
119 ARMV7M_R1
= ARMV7M_REGSEL_R1
,
120 ARMV7M_R2
= ARMV7M_REGSEL_R2
,
121 ARMV7M_R3
= ARMV7M_REGSEL_R3
,
123 ARMV7M_R4
= ARMV7M_REGSEL_R4
,
124 ARMV7M_R5
= ARMV7M_REGSEL_R5
,
125 ARMV7M_R6
= ARMV7M_REGSEL_R6
,
126 ARMV7M_R7
= ARMV7M_REGSEL_R7
,
128 ARMV7M_R8
= ARMV7M_REGSEL_R8
,
129 ARMV7M_R9
= ARMV7M_REGSEL_R9
,
130 ARMV7M_R10
= ARMV7M_REGSEL_R10
,
131 ARMV7M_R11
= ARMV7M_REGSEL_R11
,
133 ARMV7M_R12
= ARMV7M_REGSEL_R12
,
134 ARMV7M_R13
= ARMV7M_REGSEL_R13
,
135 ARMV7M_R14
= ARMV7M_REGSEL_R14
,
136 ARMV7M_PC
= ARMV7M_REGSEL_PC
,
138 ARMV7M_xPSR
= ARMV7M_REGSEL_xPSR
,
139 ARMV7M_MSP
= ARMV7M_REGSEL_MSP
,
140 ARMV7M_PSP
= ARMV7M_REGSEL_PSP
,
142 /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
144 /* A block of container and contained registers follows:
145 * THE ORDER IS IMPORTANT to the end of the block ! */
146 /* working register for packing/unpacking special regs, hidden from gdb */
147 ARMV7M_PMSK_BPRI_FLTMSK_CTRL
,
149 /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
150 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
151 * cache only and are not flushed to CPU HW register.
152 * To trigger write to CPU HW register, add
153 * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
159 /* The end of block of container and contained registers */
161 /* ARMv8-M specific registers */
171 /* A block of container and contained registers follows:
172 * THE ORDER IS IMPORTANT to the end of the block ! */
173 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S
,
178 /* The end of block of container and contained registers */
180 /* A block of container and contained registers follows:
181 * THE ORDER IS IMPORTANT to the end of the block ! */
182 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS
,
187 /* The end of block of container and contained registers */
189 /* 64bit Floating-point registers */
207 /* Floating-point status register */
210 /* for convenience add registers' block delimiters */
212 ARMV7M_CORE_FIRST_REG
= ARMV7M_R0
,
213 ARMV7M_CORE_LAST_REG
= ARMV7M_xPSR
,
214 ARMV7M_FPU_FIRST_REG
= ARMV7M_D0
,
215 ARMV7M_FPU_LAST_REG
= ARMV7M_FPSCR
,
216 ARMV8M_FIRST_REG
= ARMV8M_MSP_NS
,
217 ARMV8M_LAST_REG
= ARMV8M_CONTROL_NS
,
227 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
229 #define ARMV7M_COMMON_MAGIC 0x2A452A45
231 struct armv7m_common
{
235 int exception_number
;
237 /* AP this processor is connected to in the DAP */
238 struct adiv5_ap
*debug_ap
;
243 /* hla_target uses a high level adapter that does not support all functions */
246 struct armv7m_trace_config trace_config
;
248 /* Direct processor core register read and writes */
249 int (*load_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t *value
);
250 int (*store_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t value
);
252 int (*examine_debug_reason
)(struct target
*target
);
253 int (*post_debug_entry
)(struct target
*target
);
255 void (*pre_restore_context
)(struct target
*target
);
258 static inline bool is_armv7m(const struct armv7m_common
*armv7m
)
260 return armv7m
->common_magic
== ARMV7M_COMMON_MAGIC
;
264 * @returns the pointer to the target specific struct
265 * without matching a magic number.
266 * Use in target specific service routines, where the correct
267 * type of arch_info is certain.
269 static inline struct armv7m_common
*
270 target_to_armv7m(struct target
*target
)
272 return container_of(target
->arch_info
, struct armv7m_common
, arm
);
276 * @returns the pointer to the target specific struct
277 * or NULL if the magic number does not match.
278 * Use in a flash driver or any place where mismatch of the arch_info
281 static inline struct armv7m_common
*
282 target_to_armv7m_safe(struct target
*target
)
287 if (!target
->arch_info
)
290 /* Check the parent type first to prevent peeking memory too far
291 * from arch_info pointer */
292 if (!is_arm(target_to_arm(target
)))
295 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
296 if (!is_armv7m(armv7m
))
302 struct armv7m_algorithm
{
305 enum arm_mode core_mode
;
307 uint32_t context
[ARMV7M_LAST_REG
]; /* ARMV7M_NUM_REGS */
310 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
);
311 void armv7m_free_reg_cache(struct target
*target
);
313 enum armv7m_mode
armv7m_number_to_mode(int number
);
314 int armv7m_mode_to_number(enum armv7m_mode mode
);
316 int armv7m_arch_state(struct target
*target
);
317 int armv7m_get_gdb_reg_list(struct target
*target
,
318 struct reg
**reg_list
[], int *reg_list_size
,
319 enum target_register_class reg_class
);
321 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
);
323 int armv7m_run_algorithm(struct target
*target
,
324 int num_mem_params
, struct mem_param
*mem_params
,
325 int num_reg_params
, struct reg_param
*reg_params
,
326 target_addr_t entry_point
, target_addr_t exit_point
,
327 int timeout_ms
, void *arch_info
);
329 int armv7m_start_algorithm(struct target
*target
,
330 int num_mem_params
, struct mem_param
*mem_params
,
331 int num_reg_params
, struct reg_param
*reg_params
,
332 target_addr_t entry_point
, target_addr_t exit_point
,
335 int armv7m_wait_algorithm(struct target
*target
,
336 int num_mem_params
, struct mem_param
*mem_params
,
337 int num_reg_params
, struct reg_param
*reg_params
,
338 target_addr_t exit_point
, int timeout_ms
,
341 int armv7m_invalidate_core_regs(struct target
*target
);
343 int armv7m_restore_context(struct target
*target
);
345 uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id
);
347 bool armv7m_map_reg_packing(unsigned int arm_reg_id
,
348 unsigned int *reg32_id
, uint32_t *offset
);
350 int armv7m_checksum_memory(struct target
*target
,
351 target_addr_t address
, uint32_t count
, uint32_t *checksum
);
352 int armv7m_blank_check_memory(struct target
*target
,
353 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
);
355 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
);
357 extern const struct command_registration armv7m_command_handlers
[];
359 #endif /* OPENOCD_TARGET_ARMV7M_H */
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