tcl/target/esp32s2.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 #
   3 # The ESP32-S2 only supports JTAG.
   4 transport select jtag
   5
   6 set CPU_MAX_ADDRESS 0xFFFFFFFF
   7 source [find bitsbytes.tcl]
   8 source [find memory.tcl]
   9 source [find mmr_helpers.tcl]
  10 # Source the ESP common configuration file
  11 source [find target/esp_common.cfg]
  12
  13 if { [info exists CHIPNAME] } {
  14         set _CHIPNAME $CHIPNAME
  15 } else {
  16         set _CHIPNAME esp32s2
  17 }
  18
  19 if { [info exists CPUTAPID] } {
  20         set _CPUTAPID $CPUTAPID
  21 } else {
  22         set _CPUTAPID 0x120034e5
  23 }
  24
  25 set _TARGETNAME $_CHIPNAME
  26 set _CPUNAME cpu
  27 set _TAPNAME $_CHIPNAME.$_CPUNAME
  28
  29 jtag newtap $_CHIPNAME $_CPUNAME -irlen 5 -expected-id $_CPUTAPID
  30
  31 proc esp32s2_memprot_is_enabled { } {
  32         # IRAM0, DPORT_PMS_PRO_IRAM0_0_REG
  33         if { [get_mmr_bit 0x3f4c1010 0] != 0 } {
  34                 return 1
  35         }
  36         # DRAM0, DPORT_PMS_PRO_DRAM0_0_REG
  37         if { [get_mmr_bit 0x3f4c1028 0] != 0 } {
  38                 return 1
  39         }
  40         # PERI1, DPORT_PMS_PRO_DPORT_0_REG
  41         if { [get_mmr_bit 0x3f4c103c 0] != 0 } {
  42                 return 1
  43         }
  44         # PERI2, DPORT_PMS_PRO_AHB_0_REG
  45         if { [get_mmr_bit 0x3f4c105c 0] != 0 } {
  46                 return 1
  47         }
  48         return 0
  49 }
  50
  51 target create $_TARGETNAME esp32s2 -endian little -chain-position $_TAPNAME
  52
  53 $_TARGETNAME configure -event gdb-attach {
  54         # necessary to auto-probe flash bank when GDB is connected and generate proper memory map
  55         halt 1000
  56         if { [esp32s2_memprot_is_enabled] } {
  57                 # 'reset halt' to disable memory protection and allow flasher to work correctly
  58                 echo "Memory protection is enabled. Reset target to disable it..."
  59                 reset halt
  60         }
  61 }
  62
  63 xtensa maskisr on
  64
  65 $_TARGETNAME configure -event examine-end {
  66         # Need to enable to set 'semihosting_basedir'
  67         arm semihosting enable
  68         arm semihosting_resexit enable
  69         if { [info exists _SEMIHOST_BASEDIR] } {
  70                 if { $_SEMIHOST_BASEDIR != "" } {
  71                         arm semihosting_basedir $_SEMIHOST_BASEDIR
  72                 }
  73         }
  74 }
  75
  76 $_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
  77
  78 gdb_breakpoint_override hard
  79
  80 source [find target/xtensa-core-esp32s2.cfg]