tcl/target/gd32e23x.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for GigaDevice gd32e23x Cortex-M23 Series
   4
   5 # https://www.gigadevice.com/microcontroller/gd32e230c8t6/
   6
   7 #
   8 # gd32e23x devices support SWD transports only.
   9 #
  10 source [find target/swj-dp.tcl]
  11 source [find mem_helper.tcl]
  12
  13 if { [info exists CHIPNAME] } {
  14    set _CHIPNAME $CHIPNAME
  15 } else {
  16    set _CHIPNAME gd32e23x
  17 }
  18
  19 # Work-area is a space in RAM used for flash programming
  20 # By default use 4kB (as found on some GD32E230s)
  21 if { [info exists WORKAREASIZE] } {
  22    set _WORKAREASIZE $WORKAREASIZE
  23 } else {
  24    set _WORKAREASIZE 0x1000
  25 }
  26
  27 # Allow overriding the Flash bank size
  28 if { [info exists FLASH_SIZE] } {
  29     set _FLASH_SIZE $FLASH_SIZE
  30 } else {
  31     # autodetect size
  32     set _FLASH_SIZE 0
  33 }
  34
  35 #jtag scan chain
  36 if { [info exists CPUTAPID] } {
  37    set _CPUTAPID $CPUTAPID
  38 } else {
  39    # this is the SW-DP tap id not the jtag tap id
  40    set _CPUTAPID 0x0bf11477
  41 }
  42
  43 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  44 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  45
  46 set _TARGETNAME $_CHIPNAME.cpu
  47 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
  48
  49 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  50
  51 # flash size will be probed
  52 set _FLASHNAME $_CHIPNAME.flash
  53 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
  54
  55 # SWD speed (may be updated to higher value in board config file)
  56 adapter speed 1000
  57
  58 reset_config srst_nogate
  59
  60 if {![using_hla]} {
  61     # if srst is not fitted use SYSRESETREQ to
  62     # perform a soft reset
  63     cortex_m reset_config sysresetreq
  64 }
  65
  66 $_TARGETNAME configure -event examine-end {
  67         # Debug clock enable
  68         # RCU_APB2EN |= DBGMCUEN
  69         mmw 0x40021018 0x00400000 0
  70
  71         # Stop watchdog counters during halt
  72         # DBG_CTL0 |= WWDGT_HOLD | FWDGT_HOLD | STB_HOLD | DSLP_HOLD | SLP_HOLD
  73         mmw 0x40015804 0x00000307 0
  74 }