1 # Freescale i.MX6 series single/dual/quad core processor
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 # CoreSight Debug Access Port
10 if { [info exists DAP_TAPID] } {
11 set _DAP_TAPID $DAP_TAPID
13 set _DAP_TAPID 0x4ba00477
16 jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
17 -expected-id $_DAP_TAPID
20 jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
22 # System JTAG Controller
23 if { [info exists SJC_TAPID] } {
24 set _SJC_TAPID $SJC_TAPID
26 set _SJC_TAPID 0x0191c01d
28 set _SJC_TAPID2 0x2191c01d
29 set _SJC_TAPID3 0x2191e01d
30 set _SJC_TAPID4 0x1191c01d
32 jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
33 -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
34 -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
36 # GDB target: Cortex-A9, using DAP, configuring only one core
37 # Base addresses of cores:
42 set _TARGETNAME $_CHIPNAME.cpu.0
43 target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
44 -coreid 0 -dbgbase 0x82150000
46 # some TCK cycles are required to activate the DEBUG power domain
47 jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
49 proc imx6_dbginit {target} {
50 # General Cortex A8/A9 debug initialisation
54 # Slow speed to be sure it will work
56 $_TARGETNAME configure -event reset-start { adapter_khz 1000 }
58 $_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
59 $_TARGETNAME configure -event gdb-attach { halt }
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