tcl/target/npcx.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for Nuvoton NPCX Cortex-M4 Series
   4
   5 # Adapt based on what transport is active.
   6 source [find target/swj-dp.tcl]
   7
   8 # Set Chipname
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME NPCX_M4
  13 }
  14
  15 # SWD DAP ID of Nuvoton NPCX Cortex-M4.
  16 if { [info exists CPUDAPID ] } {
  17    set _CPUDAPID $CPUDAPID
  18 } else {
  19    set _CPUDAPID 0x4BA00477
  20 }
  21
  22 # Work-area is a space in RAM used for flash programming
  23 # By default use 32kB
  24 if { [info exists WORKAREASIZE] } {
  25    set _WORKAREASIZE $WORKAREASIZE
  26 } else {
  27    set _WORKAREASIZE 0x8000
  28 }
  29
  30 # Debug Adapter Target Settings
  31 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
  32 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  33 set _TARGETNAME $_CHIPNAME.cpu
  34 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
  35
  36 $_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  37
  38 # Initial JTAG/SWD speed
  39 # For safety purposes, set for the lowest cpu clock configuration
  40 # 4MHz / 6 = 666KHz, so use 600KHz for it
  41 adapter speed 600
  42
  43 # For safety purposes, set for the lowest cpu clock configuration
  44 $_TARGETNAME configure -event reset-start {adapter speed 600}
  45
  46 # use sysresetreq to perform a system reset
  47 cortex_m reset_config sysresetreq
  48
  49 # flash configuration
  50 set _FLASHNAME $_CHIPNAME.flash
  51 flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME