1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # common script for stm32l5x and stm32u5x families
5 # Work-area is a space in RAM used for flash programming
7 if { [info exists WORKAREASIZE] } {
8 set _WORKAREASIZE $WORKAREASIZE
10 set _WORKAREASIZE 0x10000
14 if { [info exists CPUTAPID] } {
15 set _CPUTAPID $CPUTAPID
18 # STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
19 # STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
20 # Corresponds to Cortex®-M33 JTAG debug port ID code
21 set _CPUTAPID 0x0ba04477
23 # SWD IDCODE (single drop, arm)
24 set _CPUTAPID 0x0be12477
28 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
29 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
32 jtag newtap $_CHIPNAME bs -irlen 5
35 set _TARGETNAME $_CHIPNAME.cpu
36 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
38 # use non-secure RAM by default
39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
41 # create sec/ns flash and otp memories (sizes will be probed)
42 flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
43 flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
44 flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
46 # Common knowledge tells JTAG speed should be <= F_CPU/6.
47 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
50 # Note that there is a pretty wide band where things are
51 # more or less stable, see http://review.openocd.org/3366
54 adapter srst delay 100
59 reset_config srst_nogate
62 echo "Warn : The selected adapter does not support debugging this device in secure mode"
64 # if srst is not fitted use SYSRESETREQ to
65 # perform a soft reset
66 cortex_m reset_config sysresetreq
69 proc stm32x5x_is_secure {} {
70 # read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
71 set DSCSR [mrw 0xE000EE08]
72 return [expr {($DSCSR & (1 << 16)) != 0}]
75 proc stm32x5x_ahb_ap_non_secure_access {} {
76 # in HLA mode, non-secure debugging is possible without changing the AP CSW
78 # SPROT=1=Non Secure access, Priv=1
79 [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
83 proc stm32x5x_ahb_ap_secure_access {} {
85 # SPROT=0=Secure access, Priv=1
86 [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
90 $_TARGETNAME configure -event reset-start {
91 # Reset clock is MSI (4 MHz)
95 $_TARGETNAME configure -event examine-end {
96 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
97 mmw 0xE0044004 0x00000006 0
99 # Stop watchdog counters during halt
100 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
101 mmw 0xE0044008 0x00001800 0
104 $_TARGETNAME configure -event halted {
105 set secure [stm32x5x_is_secure]
108 set secure_str "Secure"
109 stm32x5x_ahb_ap_secure_access
111 set secure_str "Non-Secure"
112 stm32x5x_ahb_ap_non_secure_access
115 # print the secure state only when it changes
116 set _TARGETNAME [target current]
117 global $_TARGETNAME.secure
119 if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
120 echo "CPU in $secure_str state"
121 # update saved security state
122 set $_TARGETNAME.secure $secure
126 $_TARGETNAME configure -event gdb-flash-erase-start {
127 set use_secure_workarea 0
128 # check if FLASH_OPTR.TZEN is enabled
129 set FLASH_OPTR [mrw 0x40022040]
130 if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
131 echo "TZEN option bit disabled"
132 stm32x5x_ahb_ap_non_secure_access
134 stm32x5x_ahb_ap_secure_access
135 echo "TZEN option bit enabled"
137 # check if FLASH_OPTR.RDP is not Level 0.5
138 if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
139 set use_secure_workarea 1
143 set _TARGETNAME [target current]
144 set workarea_addr [$_TARGETNAME cget -work-area-phys]
145 echo "workarea_addr $workarea_addr"
147 if {$use_secure_workarea} {
148 set workarea_addr [expr {$workarea_addr | 0x10000000}]
150 set workarea_addr [expr {$workarea_addr & ~0x10000000}]
153 $_TARGETNAME configure -work-area-phys $workarea_addr
156 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
158 lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
159 proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
162 # Set TRACE_EN and TRACE_IOEN in DBGMCU_CR
163 # Leave TRACE_MODE untouched (defaults to async).
164 # When using sync change this value accordingly to configure trace pins
166 mmw 0xE0044004 0x00000030 0
169 $_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"