aarch64: allow reading TTBR register when halted in EL0

There's no access to TTBR in EL0. Circumvent by moving the PE to EL1
before reading, and switch back to original mode afterwards.

Change-Id: I22891b958d3d7e6fad1cb27183c192d975d63d89
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>

diff --git a/src/target/armv8.c b/src/target/armv8.c
index b55c153f5a6f92366e1e3d78d6a5ba1593ac8e42..089982e91f28ccc211515dc9b3aefaaabb87ecc0 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -737,6 +737,8 @@ static __unused int armv8_read_ttbcr(struct target *target)
                armv8->page_size = (ttbcr >> 14) & 3;
                break;
        case SYSTEM_CUREL_EL0:
+               armv8_dpm_modeswitch(dpm, ARMV8_64_EL1H);
+               /* fall through */
        case SYSTEM_CUREL_EL1:
                retval = dpm->instr_read_data_r0_64(dpm,
                                ARMV8_MRS(SYSTEM_TCR_EL1, 0),
@@ -764,6 +766,7 @@ static __unused int armv8_read_ttbcr(struct target *target)
                LOG_INFO("TTBR0 access above %" PRIx64, (uint64_t)(armv8->armv8_mmu.ttbr0_mask));
 
 done:
+       armv8_dpm_modeswitch(dpm, ARM_MODE_ANY);
        dpm->finish(dpm);
        return retval;
 }