}
}
+proc _get_rtos_type_for_cpu { target_name } {
+ if { [info exists ::RTOS($target_name)] } {
+ return $::RTOS($target_name)
+ }
+ return none
+}
+
set _CHIPNAME $_soc
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
# sysctrl is always present
cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
$_TARGETNAME.sysctrl configure -event reset-assert { }
proc sysctrl_up {} {
-baseaddr [lindex $ARMV8_CTIBASE $_core]
target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
- -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
+ -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
# inactive core examination will fail - wait till startup of additional core
target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
- -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
+ -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
$_TARGETNAME.$_r5_name configure -event gdb-attach {
_cpu_no_smp_up
if { $_gp_mcu_cores != 0 } {
cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
- target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+ target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+ -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
$_TARGETNAME.gp_mcu configure -event reset-assert { }
proc gp_mcu_up {} {