For historical reasons, no license information was added to the
tcl files. This makes trivial adding the SPDX tag through script:
fgrep -rL SPDX tcl | while read a;do \
sed -i '1{i# SPDX-License-Identifier: GPL-2.0-or-later\n
}' $a;done
With no specific license information from the author, let's extend
the OpenOCD project license GPL-2.0-or-later to the files.
Change-Id: Ief3da306a6e1978de7dfb8f552f9ff23151f9944
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7030
Tested-by: jenkins
54 files changed:
+# SPDX-License-Identifier: GPL-2.0-or-later
+
#----------------------------------------
# Purpose - Create some $BIT variables
# Create $K and $M variables
#----------------------------------------
# Purpose - Create some $BIT variables
# Create $K and $M variables
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ]
global AIC_SMR
set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ]
set AIC_SMR [expr {$AT91C_BASE_AIC + 0x00000000} ]
global AIC_SMR
set AIC_SVR [expr {$AT91C_BASE_AIC + 0x00000080} ]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set PIO_PER 0x00 ;# Enable Register
set PIO_PDR 0x04 ;# Disable Register
set PIO_PSR 0x08 ;# Status Register
set PIO_PER 0x00 ;# Enable Register
set PIO_PDR 0x04 ;# Disable Register
set PIO_PSR 0x08 ;# Status Register
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register
set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register
set AT91_PMC_SCER [expr {$AT91_PMC + 0x00}] ;# System Clock Enable Register
set AT91_PMC_SCDR [expr {$AT91_PMC + 0x04}] ;# System Clock Disable Register
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set AT91_RSTC_CR [expr {$AT91_RSTC + 0x00}] ;# Reset Controller Control Register
set AT91_RSTC_PROCRST [expr {1 << 0}] ;# Processor Reset
set AT91_RSTC_PERRST [expr {1 << 2}] ;# Peripheral Reset
set AT91_RSTC_CR [expr {$AT91_RSTC + 0x00}] ;# Reset Controller Control Register
set AT91_RSTC_PROCRST [expr {1 << 0}] ;# Processor Reset
set AT91_RSTC_PERRST [expr {1 << 2}] ;# Peripheral Reset
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set AT91_WDT_CR [expr {$AT91_WDT + 0x00}] ;# Watchdog Control Register
set AT91_WDT_WDRSTT [expr {1 << 0}] ;# Restart
set AT91_WDT_KEY [expr {0xa5 << 24}] ;# KEY Password
set AT91_WDT_CR [expr {$AT91_WDT + 0x00}] ;# Watchdog Control Register
set AT91_WDT_WDRSTT [expr {1 << 0}] ;# Restart
set AT91_WDT_KEY [expr {0xa5 << 24}] ;# KEY Password
+# SPDX-License-Identifier: GPL-2.0-or-later
+
source [find bitsbytes.tcl]
source [find cpu/arm/arm7tdmi.tcl]
source [find memory.tcl]
source [find bitsbytes.tcl]
source [find cpu/arm/arm7tdmi.tcl]
source [find memory.tcl]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
source [find bitsbytes.tcl]
source [find cpu/arm/arm7tdmi.tcl]
source [find memory.tcl]
source [find bitsbytes.tcl]
source [find cpu/arm/arm7tdmi.tcl]
source [find memory.tcl]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
#
# Peripheral identifiers/interrupts.
#
#
# Peripheral identifiers/interrupts.
#
+# SPDX-License-Identifier: GPL-2.0-or-later
set AT91_MATRIX_MCFG [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register #
set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
set AT91_MATRIX_MCFG [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register #
set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
+# SPDX-License-Identifier: GPL-2.0-or-later
+
#
# Peripheral identifiers/interrupts.
#
#
# Peripheral identifiers/interrupts.
#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0
set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1
set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2
set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0
set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1
set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2
+# SPDX-License-Identifier: GPL-2.0-or-later
+
uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
+# SPDX-License-Identifier: GPL-2.0-or-later
# SDRAM Controller (SDRAMC) registers
set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register
# SDRAM Controller (SDRAMC) registers
set AT91_SDRAMC_MR [expr {$AT91_SDRAMC + 0x00}] ;# SDRAM Controller Mode Register
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set AT91_SMC_READMODE [expr {1 << 0}] ;# Read Mode
set AT91_SMC_WRITEMODE [expr {1 << 1}] ;# Write Mode
set AT91_SMC_EXNWMODE [expr {3 << 4}] ;# NWAIT Mode
set AT91_SMC_READMODE [expr {1 << 0}] ;# Read Mode
set AT91_SMC_WRITEMODE [expr {1 << 1}] ;# Write Mode
set AT91_SMC_EXNWMODE [expr {3 << 4}] ;# NWAIT Mode
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# External Memory Map
set AT91_CHIPSELECT_0 0x10000000
set AT91_CHIPSELECT_1 0x20000000
# External Memory Map
set AT91_CHIPSELECT_0 0x10000000
set AT91_CHIPSELECT_1 0x20000000
+# SPDX-License-Identifier: GPL-2.0-or-later
if [info exists AT91C_MAINOSC_FREQ] {
# user set this... let it be.
if [info exists AT91C_MAINOSC_FREQ] {
# user set this... let it be.
+# SPDX-License-Identifier: GPL-2.0-or-later
set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
set RTTC_RTMR [expr {$AT91C_BASE_RTTC + 0x00}]
set RTTC_RTAR [expr {$AT91C_BASE_RTTC + 0x04}]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Setup register
#
# ncs_read_setup
# Setup register
#
# ncs_read_setup
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# the DBGU and USARTs are 'almost' indentical'
set DBGU_CR [expr {$AT91C_BASE_DBGU + 0x00000000}]
set DBGU_MR [expr {$AT91C_BASE_DBGU + 0x00000004}]
# the DBGU and USARTs are 'almost' indentical'
set DBGU_CR [expr {$AT91C_BASE_DBGU + 0x00000000}]
set DBGU_MR [expr {$AT91C_BASE_DBGU + 0x00000004}]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Quirks to bypass missing SRST on JTAG connector
# EVALSPEAr310 Rev. 2.0
# http://www.st.com/spear
# Quirks to bypass missing SRST on JTAG connector
# EVALSPEAr310 Rev. 2.0
# http://www.st.com/spear
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Generic init scripts for all ST SPEAr3xx family
# http://www.st.com/spear
#
# Generic init scripts for all ST SPEAr3xx family
# http://www.st.com/spear
#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Init scripts to configure DDR controller of SPEAr3xx
# http://www.st.com/spear
# Original values taken from XLoader source code
# Init scripts to configure DDR controller of SPEAr3xx
# http://www.st.com/spear
# Original values taken from XLoader source code
+# SPDX-License-Identifier: GPL-2.0-or-later
+
source [find bitsbytes.tcl]
source [find cpu/arm/cortex_m3.tcl]
source [find memory.tcl]
source [find bitsbytes.tcl]
source [find cpu/arm/cortex_m3.tcl]
source [find memory.tcl]
+# SPDX-License-Identifier: GPL-2.0-or-later
set RCC_CR [expr {$RCC_BASE + 0x00}]
set RCC_CFGR [expr {$RCC_BASE + 0x04}]
set RCC_CR [expr {$RCC_BASE + 0x00}]
set RCC_CFGR [expr {$RCC_BASE + 0x04}]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# /* Peripheral and SRAM base address in the alias region */
set PERIPH_BB_BASE 0x42000000
set SRAM_BB_BASE 0x22000000
# /* Peripheral and SRAM base address in the alias region */
set PERIPH_BB_BASE 0x42000000
set SRAM_BB_BASE 0x22000000
+# SPDX-License-Identifier: GPL-2.0-or-later
+
source [find chip/ti/lm3s/lm3s_regs.tcl]
source [find chip/ti/lm3s/lm3s_regs.tcl]
+# SPDX-License-Identifier: GPL-2.0-or-later
+
#*****************************************************************************
#
# The following are defines for the System Control register addresses.
#*****************************************************************************
#
# The following are defines for the System Control register addresses.
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Altera MAXV 5M24OZ/5M570Z CPLD
# see MAX V Device Handbook
# Table 6-3: 32-Bit MAX V Device IDCODE
# Altera MAXV 5M24OZ/5M570Z CPLD
# see MAX V Device Handbook
# Table 6-3: 32-Bit MAX V Device IDCODE
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Altera MAXII EPM240T100C CPLD
if { [info exists CHIPNAME] } {
# Altera MAXII EPM240T100C CPLD
if { [info exists CHIPNAME] } {
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set _USER1 0x02
if { [info exists JTAGSPI_IR] } {
set _USER1 0x02
if { [info exists JTAGSPI_IR] } {
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Lattice ispMACH 4000ZE family, device LC4032ZE
# just configure a tap
jtag newtap LC4032ZE tap -irlen 8 -expected-id 0x01806043
# Lattice ispMACH 4000ZE family, device LC4032ZE
# just configure a tap
jtag newtap LC4032ZE tap -irlen 8 -expected-id 0x01806043
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# xilinx spartan6
# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
# xilinx spartan6
# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# xilinx series 7 (artix, kintex, virtex)
# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
# xilinx series 7 (artix, kintex, virtex)
# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+# SPDX-License-Identifier: GPL-2.0-or-later
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
+# SPDX-License-Identifier: GPL-2.0-or-later
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
+# SPDX-License-Identifier: GPL-2.0-or-later
+
#xilinx coolrunner xcr3256
#simple device - just configure a tap
jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id 0x0494c093
#xilinx coolrunner xcr3256
#simple device - just configure a tap
jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id 0x0494c093
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Xilinx Ultrascale (Kintex, Virtex, Zynq)
# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
# Xilinx Ultrascale (Kintex, Virtex, Zynq)
# https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set CPU_TYPE arm
set CPU_NAME arm7tdmi
set CPU_ARCH armv4t
set CPU_TYPE arm
set CPU_NAME arm7tdmi
set CPU_ARCH armv4t
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set CPU_TYPE arm
set CPU_NAME arm920
set CPU_ARCH armv4t
set CPU_TYPE arm
set CPU_NAME arm920
set CPU_ARCH armv4t
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set CPU_TYPE arm
set CPU_NAME arm946
set CPU_ARCH armv5te
set CPU_TYPE arm
set CPU_NAME arm946
set CPU_ARCH armv5te
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set CPU_TYPE arm
set CPU_NAME arm966
set CPU_ARCH armv5te
set CPU_TYPE arm
set CPU_NAME arm966
set CPU_ARCH armv5te
+# SPDX-License-Identifier: GPL-2.0-or-later
+
set CPU_TYPE arm
set CPU_NAME cortex_m3
set CPU_ARCH armv7
set CPU_TYPE arm
set CPU_NAME cortex_m3
set CPU_ARCH armv7
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# see MAX 10 FPGA Device Architecture
# Table 3-1: IDCODE Information for MAX 10 Devices
# Intel MAX 10M02 0x31810dd
# see MAX 10 FPGA Device Architecture
# Table 3-1: IDCODE Information for MAX 10 Devices
# Intel MAX 10M02 0x31810dd
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Altera Cyclone III EP3C10
# see Cyclone III Device Handbook, Volume 1;
# Table 14–5. 32-Bit Cyclone III Device IDCODE
# Altera Cyclone III EP3C10
# see Cyclone III Device Handbook, Volume 1;
# Table 14–5. 32-Bit Cyclone III Device IDCODE
+# SPDX-License-Identifier: GPL-2.0-or-later
+
proc xilinx_dna_addr {chip} {
array set addrs {
Spartan6 0x30
proc xilinx_dna_addr {chip} {
array set addrs {
Spartan6 0x30
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Xilinx XADC support for 7 Series FPGAs
#
# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
# Xilinx XADC support for 7 Series FPGAs
#
# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Helper for common memory read/modify/write procedures
# mrw: "memory read word", returns value of $reg
# Helper for common memory read/modify/write procedures
# mrw: "memory read word", returns value of $reg
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# MEMORY
#
# All Memory regions have two components.
# MEMORY
#
# All Memory regions have two components.
+# SPDX-License-Identifier: GPL-2.0-or-later
proc proc_exists { NAME } {
set n [info commands $NAME]
proc proc_exists { NAME } {
set n [info commands $NAME]
+# SPDX-License-Identifier: GPL-2.0-or-later
add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
+# SPDX-License-Identifier: GPL-2.0-or-later
+
adapter srst delay 200
jtag_ntrst_delay 200
adapter srst delay 200
jtag_ntrst_delay 200
+# SPDX-License-Identifier: GPL-2.0-or-later
+
echo "\n\nFirmware recovery helpers"
echo "Use -c firmware_help to get help\n"
echo "\n\nFirmware recovery helpers"
echo "Use -c firmware_help to get help\n"
+# SPDX-License-Identifier: GPL-2.0-or-later
+
# Algorithms by Michael Barr, released into public domain
# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser
# Algorithms by Michael Barr, released into public domain
# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser
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Code Review / openocd.git / commitdiff